Showing papers by "Codex Corporation published in 1993"

Voltage controlled oscillator operating with digital controlled loads in a phase lock loop

Abstract: A phase lock loop (16) operates independent of temperature and process variation by digitally loading a VCO (22) until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors (162-166, 174-180, 182-188) to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit (32) sets the loop node voltage to V DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector (34) monitors the output frequency of the VCO and passes control signals to a load control circuit to (36) activate digital loads (38) and slow down the VCO to the desired operating frequency.

Advanced Modulation Techniques for V.Fast

Abstract: An overview is provided of the modulation techniques that are being considered for a new voiceband modem Recommendation, nicknamed V.fast. These techniques include adaptive bandwidth operation for automatically selecting the transmission band, multi-dimensional trollis coded modulation for higher coding gain, constellation shaping for higher shaping gain, precoding and pre-emphasis for advanced equalization, and warping for resistance against signal-dependent impairments. Simulation results are presented to illustrate performance. By adaptively selecting an appropriate combination of these modulation techniques based on line conditions, V.fast modems are expected to double the maximum data rate of standard modems.

Ballot theorems applied to the transient analysis of nD/D/1 queues

Abstract: The problem of transporting constant-bit-rate (CBR) traffic through a packet network is analyzed. In the system considered, CBR traffic is packetized and packets from several similar sources are multiplexed on a transmission link. The bit streams are recreated at the receiving end by demultiplexing the packets and then playing out the packets of each CBR stream. Traffic fluctuations may cause gaps to appear in the playout process. Their frequency can be reduced by adding a smoothing delay to each stream. The queueing system analyzed has periodic arrivals and deterministic service times. A method of analysis, based on the ballot theorems of Takacs (1967), is presented to provide steady-state delay distributions as well as a transient analysis of the system to predict the statistics of the time for a gap to develop in the CBR stream as a function of the smoothing delay. >

System and method for call-by-call source routing with rule-based fallbacks

Abstract: A fallback strategy for a system (700) and method (200) is provided for rerouting a call that fails to be established utilizing a first set of constraints in a communication network system. This strategy enables the communication network system to utilize a look-around-first type of preemption that avoids unnecessary preemption and provides alternate routing for a call according to predetermined constraints selected by a user.

Circuit and method of controlling a VCO with capacitive loads

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

High frequency voltage controlled oscillator

Abstract: A phase lock loop (10) operates independent of temperature and process variation by digitally loading a VCO (12) until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors (162-166, 174-180, 182-188) to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit (32) sets the loop node voltage to VDD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector (34) monitors the output frequency of the VCO and passes control signals to a load control circuit (36) to activate digital loads (38) and slow down the VCO to the desired operating frequency.

Circuit and method of sensing process and temperature variation in an integrated circuit

Abstract: A voltage controlled oscillator runs at full speed to generate an output frequency dependent on temperature and process variation First and second clock signals are generated from the oscillator signal, while third and fourth clock signals are developed in response to an input clock signal The number of clock signals occurring during a first state of the third clock signal are counted for providing a plurality of output signals also indicative of the temperature and process variation The plurality of output signals compensate an input signal for the temperature and process variation for providing an output signal

Fast initialization of data-driven Nyquist in-band echo cancellers

Abstract: A echo canceller fast training scheme for data-driven Nyquist in-band echo cancellers is presented. This scheme simultaneously estimates the desired near and far echo canceller coefficients by sending a special periodic training sequence and correlating a segment of the sequence with the real echo samples. The requirements and the generation of the training sequence are discussed. It is shown that the fast training method can also provide the parameters for the fast initialization of the phase roll compensator in the echo canceller, and thus complete the fast training of the entire echo canceller. Compared to the conventional LMS training and other training methods, this scheme provides accurate estimates of the echo canceller coefficients in a significantly reduced training time. >

Device and method for automatically adjusting a phase-locked loop

Abstract: The present invention includes a phase-locked loop (PLL) parameter adjusting device (APAD) (100) that automatically adjusts a phase-locked loop as needed. The present invention enables a PLL to provide a faster tracking speed while maintaining minimal possible noise bandwidth. The PLL error signal is first integrated either during successive predetermined time periods or over successive N samples of said phase error signal. The integration signal is then applied to a limiter whose output is representative of the sign of the integration signal. Counting means (104) integrate K sign signals and provide a count value to a threshold unit (106). The threshold unit (106) provides a parameter modification signal to an automatic decision unit (108). This unit (108) provides adjusted parameters to the PLL and adjusts the value of N and/or the predetermined time period in response to said parameter modification signal and according to a predetermined strategy.

Automatic data restoral for modems

Abstract: Automatically restoring data transmission by monitoring line degradation and switching to a new line (or lines) when line quality falls below a prescribed standard. Data transmission is maintained on the leased line while communication is being established on the dial line, so as not to disrupt data transmission; communication is established across two dial lines to restore full-duplex transmission; energy is maintained on the dial lines at times when data is not being transmitted to prevent a change of channel on a dial line; a signal processor, associated memory, and analog interface circuitry provide the data restoral functions; control of the restoral procedure is handled by one modem (e.g., the calling modem), and commands are sent to the other modem over either the leased or dial lines.

Frequency range detector

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO (22) until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors (162-166, 174-180, 182-188) to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit (32) sets the loop node voltage to VDD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector (34) monitors the output frequency of the VCO and passes control signals to a load control circuit to (36) activate digital loads (38) and slow down the VCO to the desired operating frequency.

Apparatus and method using shift registers for generation of a bias voltage for a VCO in a phase locked loop

Abstract: of EP0614275A bias voltage (26) for a VCO (20) is generated by monitoring UP and DOWN control signals to a charge pump (14) and generating first and second output signals upon detecting a predetermined number of consecutive UP pulses or DOWN pulses. The first output signal causes a shift register (64) pre-loaded with a data pattern having one odd logic state to shift one bit location to left, while the second output signal moves the odd logic state one bit location to the right. The bias voltage to the VCO is selected based on the odd logic state bit location. Any variation in VCO output frequency due to intermittent ground bounce is eliminated by requiring a consecutive number of UP pulses or DOWN pulses before moving the VCO bias point.

Improved shell mapping with coded modulation

Abstract: Shell mapping is a block coding method which can support fractional bits per symbol, while providing a shaping gain in a seamless manner. In the Letter we propose a partitioning algorithm that improves the performance of shell mapping, especially in the presence of severe nonlinear distortion.

Low Complexity Lpc Quantization Using The Structured Vector Quantizer

Abstract: This paper describes the findings of a recent study on quantization of the LPC parameters, represented as the arcsine of the reflection coefficients, using the structured Vector Quantizer (SVQ). Our results show that the SVQ can reduce the bit-rate by about 12 percent, compared to a conventional scalar quantizer. The SVQ also achieves a better performance than a split-VQ at a much lower implementation complexity.

A phase lock loop

Abstract: The invention relates to A phase lock loop, comprising: first means (12) for comparing a phase difference of first and second input signals and generating first and second control signals; a charge pump (14) responsive to said first and second control signals for charging and discharging a loop node; a VCO (20) having a control input, a bias input and an output, said control input being coupled to said loop node, said output providing an oscillator signal; second means (24) for dividing down said oscillator signal into said second input signal to said first means; and third means (26) coupled for receiving said first and second control signals from said charge pump and selecting one bias transistor pair in a plurality of bias transistor pairs for generating a continuous bias control voltage as set by said one bias transistor pair to said bias input of said VCO upon detecting a predetermined number of consecutive first control signals or consecutive second control signals.