Showing papers by "Freescale Semiconductor published in 1985"

Recirculating MOS charge pump

Abstract: A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.

Removable sidewall spacer for lightly doped drain formation using two mask levels

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDS) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Conformal materials such as CVD polysilicon may also be employed for this purpose. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implantation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation.

An interface circuit for interfacing between asynchronous data in start/stop format and synchronous data

Abstract: A data interface circuit (33) for interfacing between an asynchronous data source providing data in start/stop format and a synchronous data communication channel (34, 35). The data interface circuit (33) has a transmit portion (41) and a receive portion (42) which function independently. Upon receipt of asynchronous data, the transmit portion (41) strips start and stop bits from the data and transmits the data in data frames of variable length chararcterized by beginning and ending with synchronizing idle codes. The synchronizing idle codes are transmitted in the absence of data to maintain synchronization. A code circuit (71) insures that a data word is never the same as the idle code. Similarly, upon receipt of synchronous data and idle codes, the receive portion (42) stores the data and controllably adds start and stop bits. Data in start/stop format is asynchronously provided at an output of the receive portion (42).

Method of making an integral, multiple layer antireflection coating by hydrogen ion implantation

Abstract: A process is disclosed for fabricating an improved antireflection coating on a substrate. A layer of dielectric material having a first thickness and a first index of refraction are formed overlying a substrate. The dielectric material is implanted with hydrogen to form an implanted surface region having a thickness less than the thickness of the entire layer of dielectric material. The hydrogen reduces the index of refraction of the implanted region to a value less than the index of refraction of the initial layer. The structure overlying the substrate thus includes two integral layers having different indices of refraction with the lower index of refraction, as desired, at the surface of the dielectric material. The process can be extended by further implantation to provide an increased number of distinct layers of differing index or to provide a continuum of regions of varying index of refraction.

Paged memory management unit having variable number of translation table levels

Abstract: In a paged memory management unit (PMMU), a translation control (TC) register contains a set of table indexes which define the number of bits of the logical address to be used to access the translation table at the respective levels. The TC register also contains an initial shift field which defines the number of high order bits of the logical address to be discarded before an address translation, and a page size field which defines the number of low order bits of the logical address comprising the page address. Each descriptor in each translation table contains a descriptor type field which defines whether that particular descriptor is a translation descriptor or a pointer descriptor. If a pointer descriptor is encountered at a table level other than the lowest level, the translation table walk is terminated early and the translation performed using that pointer descriptor. In general, a table may occupy either the lower or upper portions of the page in which such table is stored. Each descriptor contains a lower/upper (L/U) bit which defines the relative displacement of the next-lower table relative to the specified table address. If a table is addressed outside the appropriate range, the PMMU will not abort the table walk and bus error the access.

An interlayer contact for use in a static ram cell

Abstract: A CMOS static RAM (10), which has P channel transistors (12, 14) formed in a second polysilicon layer (39, 40), N channel transistors (11, 13, 15, 16) formed in the substrate (48), and gates of both the N channel (11, 13, 15, 16) and P channel transistors (12, 14) formed in a first polysilicon layer (29, 30, 31, 32), requires that ohmic contact be made between semiconductor material of different conductivity type. The first polysilicon layer (29, 30, 31, 32) is N-type, and the second polysilicon layer (39, 40) is P-type. Ohmic contact therebetween is achieved by providing a silicide layer (35, 36) which is between these two layers and in physical contact with both. Ohmic contact between N-type regions (32) in the substrate (48) and the second polysilicon layer (39, 40) is similarly achieved by sandwiching silicide (34, 37) therebetween.

Poly-sidewall contact semiconductor device method

Abstract: Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lower poly layer. The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. A conformal oxide is applied over the whole structure and anisotropically etched to remove the bottom portions in the hole where the poly pillar and the isolation wall are to be formed and isotropically where the single crystal pillar is to be formed. The remaining oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar. The structure may be made self-aligned and self-registering.

NPN band gap voltage reference

Abstract: A voltage reference circuit for providing a temperature compensated voltage at an output thereof comprise a pair of transistor operated at different current densities for producing a first and second voltages having complementary temperature coefficients and circuitry for combining the two voltages to produce the temperature compensated voltage. A pair of load resistors are connected to the collectors of the two transistors for sourcing currents thereto and a feedback circuit, including a differential amplifier coupled to the respective collectors, provides a feedback signal for adjusting the potential on the bases thereof to maintain different current densities in the two transistors. A bias circuit operates in conjunction with the differential amplifier to bias the same in a balanced operating state whenever the currents in the transistors are substantially equal.

Data processor execution unit which receives data with reduced instruction overhead

Abstract: A data processor execution unit is provided for coupling multiple operands to an AU in response to an operand selection portion of an instruction supplied from an instruction register. At least two operands are provided from two pluralities of registers, respectively. Additionally, a predetermined one of the operands contains encoded information for selecting one of a plurality of arithmetic operations which the AU performs. The operand containing the encoded information is coupled to an AU control decoder for use in controlling the operation of the AU. In one form, a single operand selection portion of an instruction selects a plurality of registers containing operands which the AU may utilize. In another form, one of the operands contains encoded information for use in selecting arithmetic formats of the AU.

Method of making closely spaced contacts to PN-junction using stacked polysilicon layers, differential etching and ion implantations

Abstract: A means and method is described for forming closely spaced contacts to adjacent semiconductor regions, such as the base and emitter of a bipolar transistor, so that the lateral voltage drops between the contacts and an intervening junction are minimized. The emitter and base and the contacts thereto are self-aligned. This is accomplished by a structure utilizing two poly-layers separated by one or more intermediate dielectric layers. The upper of the two poly-layers serves as a selective etching mask for defining the contact geometry and separation. The lower of the two poly-layers has one portion which becomes a poly-contact and diffusion source for the base region and a second portion which becomes a poly-contact and diffusion source for the emitter region. A single mask is used in connection with ion bombardment to alter the etch rate of portions of the poly-layers. This mask together with subsequent etch steps, defines the emitter width and location and the base-emitter contact separation. The process is self-aligning.

Method and apparatus for signed and unsigned bounds check

Abstract: A typical feature of a data processor (10) is a bounds check. A bounds check is achieved when a determination is made as to whether a check value, typically an address or datum, is within predetermined bounds. Such check values may be signed or unsigned. By requiring that the upper bound be numerically larger than the lower bound for doing a signed check, and requiring that the upper bound be logically larger than the lower bound for doing an unsigned check, the bounds check is performed by the data processor (10) without the need of receiving a signal which informs the data processor (10) in advance as to whether the check is to be signed or unsigned.

Communication receiver system having a voltage converter with an operating frequency below the receiver IF

Abstract: A communication receiver system for receiving coded signals and of the type having at least one predetermined intermediate frequency (IF) signal comprising a decoder for detecting and decoding the received coded signals and a DC/DC voltage converter circuit, connected to the decoder, for generating a voltage greater than the supply voltage of the communication receiver system at a frequency below the frequency of the IF signal. The system further comprises a frequency trim circuit, connected to the voltage converter circuit, for controlling the operating frequency of the DC/DC voltage converter circuit whereby interference with the IF signal is prevented.

Fabricating a semiconductor device with reduced gate leakage

Abstract: Gate current leakage is reduced in a submicron FET device by the deposition of an oxide layer over the gate prior to the rapid heating of the device. This is done to prevent the dopant that was implanted into the gate from collecting on the sidewalls of the gate and the oxide layer between gate and substrate. Otherwise the diffused dopant becomes the path of least resistance, thus creating current leakage from the gate to source or gate to drain.

Parasitic insensitive auto-zeroed operational amplifier

Abstract: An operational amplifier circuit which is substantially insensitive to inherent parasitic capacitance associated therewith is provided. An error voltage resulting from the parasitic capacitance is typically coupled onto a capacitor which is connected to a first input of an operational amplifier. To compensate for the error voltage, a substantially identical second error voltage is created and coupled to a second input of the operational amplifier, thereby cancelling the effects of the first error voltage.

Method and apparatus for implementing modulo arithmetic calculations

Abstract: A modulo arithmetic unit and method for providing a sum of first and second numbers is provided. In one form, a first adder calculates a first sum which is equal to the arithmetic sum of the first and second numbers. A second adder is provided for adding the first number to an offset value equal to (2 X -M), where X defines the number of bits of the number system used, M is a predetermined modulus and X and M are integers. A third adder operates in parallel with the first adder to calculate the sum of the output value of the second adder and the second operand to provide a second output sum and a carry output bit. In another form, only two adders are utilized wherein the first adder calculates a first output sum of the first and second numbers, and the second adder calculates the sum of the first output sum and the offset value. Both illustrated forms utilize a multiplexer which outputs one of the two calculated output sums depending upon whether a wraparound of an upper modulus boundary occurred.

BIMOS memory sense amplifier

Abstract: A BIMOS memory sense amplifier is provided having the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A pair of differentially connected NPN transistors are coupled for receiving a first and a second bit current from the bit lines of a memory circuit. A MOS transistor circuit is coupled to the NPN transistors and is responsive to a differential output therefrom, for buffering two NPN push-pull output transistors.

Operand size mechanism for control simplification

Abstract: A data processor having size selector in a controller for explicitly selecting the size of an operand independent of an instruction in an instruction register, together with means for selectively enabling the instruction register or other functional block, or a size selector to select the size of the operand. A size bus and a size multiplexer are also provided to route the size instructions. By using this size mechanism, the amount of sequencing and control logic is significantly reduced from prior data processors. The mechanism allows operations of different sizes to be performed during a single instruction while allowing instruction dependent sizing to be done residually.

Clocked gain stage having differential inputs and outputs

Abstract: A fully differential gain stage having high gain and common-mode feedback is provided with minimal circuitry. Differential input transistors adapted to receive differential input voltages are coupled to load transistors. During a first time period, the gain stage is placed in unity gain and the load transistors are configured as diodes. Charge storage devices are charged during the first time period with a charge which is proportional to both the current of a current supply and the physical dimensions of the load transistors. During a second time period, the charge storage devices provide a bias voltage to the load transistors which maintains the common-mode output voltage at a predetermined value. During the second time period, the gain stage is configured for high gain operation.

Integrated circuit and method for biasing an epitaxial layer.

Abstract: An integrated circuit (30) and method for biasing an impurity region, in particular an epitaxial layer (32), to a level substantially equal to a supply voltage level (Vcc) yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage (Vcc). The integrated circuit (30) and method is of especial utility in power BIMOS and other applications having the substrate (12) at or near the supply voltage level Vcc.

Method for applying material to a semiconductor wafer

Abstract: Passivation, alpha protection and other relatively thick, patterned layers are applied to semiconductor wafers by a screen printing method. Patterned emulsions carried on fine mesh stainless steel screens are tempered at elevated temperatures to harden the emulsion. The screens so prepared withstand many cycles of printing and cleaning with harsh solvents present in screenable polymers such as polyimide and rigid silicone.

Process for dielectrically isolated semiconductor structure

Abstract: A process is disclosed for controllably providing dielectrically isolated semiconductor regions having a uniform and well defined thickness. Grooves are formed in a first surface of a semiconductor substrate and then a dielectric layer is formed covering that surface and the grooves extending into the surface. A layer of backing material such as polycrystalline silicon is formed overlying the dielectric layer. A semiconductor substrate is then thinned to form a new surface with portions of the dielectric layer and backing material exposed at that surface. A semiconductor layer is epitaxially grown overlying the new surface with the semiconductor layer having a monocrystalline structure where it is grown on exposed regions of the original substrate and having a polycrystalline structure otherwise. An oxidation masking layer is formed overlying those portions of the semiconductor layer which have a monocrystalline structure. Those portions of the semiconductor layer which are not covered by the oxidation masking layer are then oxidized to form an oxide extending through the semiconductor layer to the underlying dielectric layer. This oxide plus the original dielectric layer thus surround and isolate individual regions in which a portion of the original substrate has an epitaxial layer of semiconductor material grown thereon.

Electronic switch for digital telephone

Abstract: An electronic switch for supplying power to a digital telephone which consumes substantially no power in the idle mode. A transistor for supplying power to the digital telephone is latched on in either of two situations. In the first situation, the telephone's hookswitch is closed. A second transistor turns on and maintains the first transistor on even after the hookswitch has been opened. In the second situation, a voltage pulse is applied to the input voltage conductor lines causing the first and second transistors to turn on. Again, the second transistor maintains the first transistor on. The circuit is inactivated by a sleep signal which turns off the second transistor which in turn turns off the first.

Method for enhancing the solderability of nickel layers

Abstract: Nickel layers used in electronic devices are frequently plated in solutions containing phosphorus. Residual phosphorus trapped in the plated nickel layer reduces solderability with respect to Pb-Sn solders. Voids are frequently found in the soldered joints. Solderability of such phosphorus containing nickel layers is enhanced and the number of voids is much reduced by heating the nickel surface first in an oxidizing atmosphere and then in a reducing atmosphere prior to soldering. The oxidation temperature should exceed 347° C. in order to oxidize the residual phosphorus and drive off the volatile phosphorus oxides. Hydrocarbons and volatile sulfides are also removed. The reducing step removes the non-volatile nickel oxides, leaving a clean surface for soldering which is substantially free of nickel oxide, phosphorus and phosphorus oxides, sulfides, and organics.

Reduced power sense amplifier

Abstract: A sense amplifier has a pair of differential amplifiers and a pair of current mirrors. Each of the current mirrors has a master and a slave. The slaves are used for both loads of one of the differential amplifiers, and the masters are used for both loads of the other of the differential amplifiers. The pair of current mirrors are formed of transistors of one conductivity type while the differential amplifiers are formed of transistors of another conductivity type.

Metal redistribution by rapid thermal processing

Abstract: A method for diffusing a metal dopant into a semiconductor switching device is provided by the use of a rapid thermal heating apparatus. This method provides a procedure for the selectively placing of a metal dopant in a region of the device or circuit. This aids in increasing the manufacturing yields of the switching device, and increases the number of active traps for minority carriers.

Low voltage clamp

Abstract: A low voltage clamp circuit comprises a transistor and semiconductor junction impedance circuitry for establishing an impedance such that the magnitude of a voltage applied across the emitter and collector of the transistor is clamped at a value that is less than the reverse breakdown voltage of the collector-to-emitter of the transistor if its base is shorted to the collector. The clamp circuit is suited to be manufactured in monolithic integrated circuit form and can be used to protect integrated bipolar transistors from having the reverse breakdown voltage of their emitter-base junctions exceeded.

Contact assembly for small semiconductor device

Abstract: A resilient contact assembly for contacting a semiconductor device comprises a center segment and first and second side segments. The center segment has an open-ended pocket in the end thereof for receiving, positioning and supporting the semiconductor device. The ends of the side segment are bent out of the plane of the center segment and first and second contact arms extend therefrom towards said pocket to contact the semiconductor device.

Data processor having multiple bus cycle operand cycles

Abstract: In a data processor adapted to perform operations upon operands of a given size, a bus controller (14) is provided to communicate the operands with a storage device (20) having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller (14) requesting the transfer of an operand of a particular size, the storage device (20) provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the torage device (20), the bus controller (14) may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller (14) compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller (14) provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.

Compensation circuit and method for stabilization of a circuit node by multiplication of displacement current

Abstract: A compensation circuit for stabilization of a circuit node (40) coupled to an integrated circuit substrate by a parasitic capacitance of a value C1 has a displacement current substantially equal to C1 dv/dt. A switching device (42) having a gain beta (beta) can either supply a current to, or draw a current from, the circuit node (40, 60) substantially equal to C2 beta dv/dt which is greater than the displacement current thereby obviating oscillation of an integrated circuit output due to capacitive coupling of the substrate to sensitive circuit nodes.

Circuit for reducing the row select voltage swing in a memory array

Abstract: A circuit reduces the row select voltage swing in a memory array, thereby reducing access time, power dissipation, disturb problems, glitches on the output, and alpha particle sensitivity. A row driver transistor is coupled between a first voltage source and the word line of a row of memory cells and has a base coupled to a row decode signal. A clamp circuit coupled to the base clamps a voltage on the base in accordance with a current provided by a current mirror coupled thereto. A write enable circuit is differentially connected to the current mirror and the clamp circuit for enabling the clamp circuit during a read mode for limiting the voltage swing on the word line.