Showing papers by "Freescale Semiconductor published in 2002"

Ultra wide bandwidth spread-spectrum communications system

Abstract: An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The communication system uses baseband codes formed from time shifted and inverted wavelets to encode data on a RF signal. Typical wavelet pulse durations are on the order of 100 to 1000 picoseconds with a bandwidth of approximately 8 GHz to 1 GHz, respectively. The combination of short duration wavelets and encoding techniques are used to spread the signal energy over an ultra wide frequency band such that the energy is not concentrated in any particular narrow band (e.g. VHF: 30-300 MHz or UHF: 300-1000 MHz) and is not detected by conventional narrow band receivers so it does not interfere with those communication systems. The use of pulse codes composed of time shifted and inverted wavelets gives the system according to the present invention has a spatial resolution on the order of 1 foot which is sufficient to minimize the negative effects of multipath interference and permit time domain rake processing.

Ultra wide bandwidth communications method and system

Abstract: An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The communication system uses baseband codes formed from time shifted and inverted wavelets to encode data on a RF signal. Typical wavelet pulse durations are on the order of 100 to 1000 picoseconds with a bandwidth of approximately 8 GHz to 1 GHz, respectively. The combination of short duration wavelets and encoding techniques are used to spread the signal energy over a an ultra wide frequency band such that the energy is not concentrated in any particular narrow band (e.g. VHF: 30-300 MHz or UHF: 300-1000 MHz) and is not detected by conventional narrow band receivers so it does not interfere with those communication systems. The use of pulse codes composed of time shifted and inverted wavelets gives the system according to the present invention has a spatial resolution on the order of 1 foot which is sufficient to minimize the negative effects of multipath interference and permit time domain rake processing.

Dual metal gate transistors for CMOS process

Abstract: A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

Method of operating a media access controller

Abstract: A method is provided for a remote device to monitor and communicate with a wireless network using cyclic beacons. The remote device receives a beacon (1405), which beacon includes beacon information that defines a superframe. From the beacon information, the remote device determines whether the received beacon and the associated superframe are assigned to a network device or are unassigned (1410). By receiving as many beacons as there are allowable devices in the network, the remote device can determine if the network is full (1430). If the remote device runs through all of the beacons and all indicate that their associated superframes are assigned, then the remote device determines that the network is full and performs a network-full function. If the remote device receives a beacon that indicates that its associated superframe is unassigned, it determines that the network is not full and performs an association request during the unassigned superframe (1415).

Electron optics for multi-beam electron beam lithography tool

Abstract: A charge particle optical column capable of being used in a high throughput, mutli-column, multi-beam electron beam lithography system is disclosed herein. The column has the following properties: purely electrostatic components; small column footprint (20 mm square); multiple, individually focused charge particle beams; telecentric scanning of all beams simultaneously on a wafer for increased depth of field; and conjugate blanking of the charged particle beams for reduced beam blur. An electron gun is disclosed that uses microfabricated field emission sources and a microfabricated aperture-deflector assembly. The aperture-deflector assembly acts as a perfect lens in focusing, steering and blanking a multipicity of electron beams through the back focal plane of an immersion lens located at the bottom of the column. Beam blanking can be performed using a gating signal to decrease beam blur during writing on the wafer.

Semiconductor fabrication process using transistor spacers of differing widths

Abstract: A semiconductor fabrication process is disclosed wherein a first gate (108, 114) is formed over a first portion of a semiconductor substrate (102) and a second gate (114, 108) is formed over a second portion of the substrate (102). A spacer film (118) is deposited over substrate (102) and first and second gates (108, 114). First spacers (126) are then formed on sidewalls of the second gate (114) and second spacers (136) are formed on sidewalls of first gate (108). The first and second spacers (126, 136) have different widths. The process may further include forming first source/drain regions (128) in the substrate laterally disposed on either side of the first spacers (126) and second source/drain regions (138) are formed on either side of second spacers (136). The different spacer widths may be achieved using masked first and second spacer etch processes (125, 135) having different degrees of isotropy. The spacer etch mask and the source/drain implant mask may be common such that p-channel transistors have a different spacer width than n-channel transistors.

Magnetoresistance random access memory

Abstract: A magnetoresistive tunneling junction memory cell comprises a magnetoresistive tunneling barrier (16), a bit magnetic region (15), a reference magnetic region (17), and current lines (20, 30) for inducing an applied magnetic field in the bit and reference magnetic regions. The bit magnetic region has a bit magnetic moment (43, 40,1425, 1625, 1950, 2315) that has a polarity in a bit easy axis (59, 1435) when there is no applied magnetic field. The tunneling barrier and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (10, 72, 73, 74, 75, 76). In some implementations (73, 74, 75), the reference magnetic region has a reference magnetic moment (40, 1430, 1440, 1920, 1925) that is non-parallel to the bit easy axis. In other implementations (76), the reference magnetic region has a magnetization vortex (2310) with a net reference magnetic moment that is essentially zero. An applied magnetic field changes the magnetic state of the reference magnetic region such that the magnetic state of the bit magnetic region can be determined by a magnetoresistive measurement.

Capped dual metal gate transistors for CMOS process and method for making the same

Abstract: A first gate ( 120 ) and a second gate ( 122 ) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well ( 104 ) and a p-type well ( 106 ) In a preferred embodiment, first gate ( 120 ) includes a first metal layer ( 110 ) of titanium nitride on a gate dielectric ( 108 ), a second metal layer ( 114 ) of tantalum silicon nitride and a silicon containing layer ( 116 ) of polysilicon Second gate ( 122 ) includes second metal layer ( 114 ) of a tantalum silicon nitride layer on the gate dielectric ( 108 ) and a silicon containing layer ( 116 ) of polysilicon First spacers ( 124 ) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps Since the chemistries used are selective to polysilicon, the spacers ( 124 ) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process The polysilicon cap also facilitates silicidation of the gates

Compaction scheme in NVM

Abstract: A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.

Transistor metal gate structure that minimizes non-planarity effects and method of formation

Abstract: A metal gate structure (10) is formed by depositing a gate dielectric (22), a gate electrode (24), a stop layer (26), and a metal layer (28) within a gate trench (19) and removing the portions of the layers that lie outside the gate trench (19). A first polish or etch process is used to remove a portion of the metal layer (28) selective to the stop layer (26). A second polish or etch process is used to remove portions of the gate dielectric (22), the gate electrode (24), the stop layer (26) and the metal layer (28) which lie outside the gate trench (19) after the first polish or etch process. The resulting structure increases the uniformity and non-planarity of the top surface of the metal gate structure (10).

Monitoring and control of an adaptive filter in a communication system

Abstract: A communication system having an echo canceller is disclosed. One embodiment of the echo canceller includes an adaptive filter used to provide an estimate of reflected echo which is removed from the send signal. The echo canceller may also include a near-end talker signal detector which may be used to prevent the adaptive filter from adapting when a near-end talker signal is present. The echo canceller may also include a nonlinear processor used to further reduce any residual echo and to preserve background noise. The echo canceller may also include a monitor and control unit which may be used to monitor the filter coefficients and gain of the adaptive filter to maintain stability of the echo canceller, estimate pure delay, detect a tone, and inject a training signal. The echo canceller may also include a nonadaptive filter used to reduce the length of the adaptive filter.

Semiconductor device structure and method for forming

Abstract: A semiconductor device structure has trenches of two widths or more The smallest widths are to maximize density The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels

Digital color image pre-processing

Abstract: In one embodiment, the invention involves a method for processing an image. A sensor output is provided. An automatic gain control of the sensor output is performed to generate a first output. An automatic white balance correction to the first output is performed to generate a second output. A gamma correction of the second output is performed to generate a third output. A color interpolation is performed to the third output to generate a fourth output. A low-pass spatial filtration of the fourth output is performed to generate a fifth output. A color saturation and correction of the fifth output is performed to generate a sixth output, and a high-pass spatial filtration of the sixth output is performed to generate an image output.

Multi-row leadframe

Abstract: A leadframe (20) for a semiconductor device includes a paddle ring (22) having an inner perimeter (24), an outer perimeter (26), and a cavity (28) located within the inner perimeter (24) for receiving an integrated circuit die (30). A first row of terminals (32) surrounds the outer perimeter (26) and a second row of terminals (34) surrounds the first row of terminals (32). Each of the terminals of the first row of terminals (32) is individually connected to the paddle ring (22) and each of the terminals of the second row of terminals (34) is connected to one side of a connection bar (78, 79), which is connected to one of the terminals of the first row (32) or to the paddle ring (22).

Semiconductor device and a method therefor

Abstract: A semiconductor device with dual gate electrodes (60, 50) and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric (40) are formed over a first doped region. The metal/gate stack (60, 50) comprises a metal portion (50) over the first gate dielectric (40) and a first gate portion (60) over the metal portion (50). A silicon gate (60) and a second gate dielectric (40) are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN. FIG. 5 accompanies the abstract.

Process for disengaging semiconductor die from an adhesive film

Abstract: An apparatus and method for separating a semiconductor die (303) from an adhesive tape (32) are disclosed. The apparatus includes a blade (34) mechanically coupled to a blade holder (36), wherein the blade (34) is inclined relative to the primary surface of the semiconductor die (303). The method further comprises lifting the semiconductor die (303) while it is attached to the adhesive tape (32) to assist disengagement. The blade (34) facilitates peeling of the semiconductor die (303) from the adhesive tape (32) while distributing stress exerted on the semiconductor die (303) over a larger surface area resulting in reduced die fractures (20).

Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics

Abstract: In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) (54) cell is stacked with an asymmetric tunnel device (56). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers (42, 46) separated by an insulator (44). The asymmetric tunnel device (56) is electrically connected in series with the MTJ cell and is formed by at least two conductive layers (48, 52) separated by an insulator (50). The asymmetric tunnel device may be a MIM (56), MIMIM (80) or a MIIM (70). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.

Method of fabricating a tiered structure using a multi-layered resist stack and use

Abstract: An improved and novel method of forming a tiered structure, such as a T-gate structure, including the fabrication of a stabilized resist layer that provides for the prevention of interlayer intermixing with the deposition of subsequent resist layers. The method includes patterning a base resist layer to provide for an opening which will form the stem of the tiered structure and subsequently stabilizing the resist base layer without deforming the stem opening. Next, a resist stack is deposited on an uppermost surface of the stabilized resist layer. Patterning the resist stack provides for an opening on an uppermost layer or portion, and a reentrant profile in a portion of the resist stack adjacent the stabilized resist layer. Metallization and subsequent removal of the resist layers results in a tiered structure, such as a T-gate structure, formed using only low to medium molecular weight, linear polymeric materials such as those used in positive optical resists in optical lithography.

System and method for providing device authentication in a wireless network

Abstract: A system and method are provided for authenticating a new device in a wireless network using an authentication device. First, the new device estimates the distance between the new device and the authenticating device as a first distance measurement, and sends the first distance measurement to the authentication device. The authentication device then estimates the distance between the new device and the authenticating device as a second distance measurement. The authentication device then evaluates the first and second distance measurements to determine if they meet authentication criteria and sends authentication data to the new device only if the first and second distance measurements meet the authentication criteria. These criteria can be that they do not differ by more than a set error value or that they both are below a set maximum value.

Data processing system having an adaptive priority controller

Abstract: The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing requests in a data processor (12) having a bus interface unit (32). The method includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from a second bus requesting resource (e.g. 28), and using a threshold corresponding to the first or second bus requesting resource to prioritize the first and second requests. The first and second bus requesting resources may be a push buffer (28) for a cache, a write buffer (30), or an instruction prefetch buffer (24). According to one embodiment, the bus interface unit (32) includes a priority controller (34) that receives the first and second requests, assigns the priority, and stores the threshold in a threshold register (66). The priority controller (34) may also include one or more threshold registers (66), subthreshold registers (68), and control registers (70).

Data storage system having a non-volatile IC based memory for storing user data

Abstract: A data storage system having a non IC based memory and an IC based non-volatile memory for storing user data. In one example, the IC based non-volatile memory is implemented with MRAM. Examples of non IC based memory include e.g. hard disks, tape, and compact disks. In some examples, the IC based memory is utilized to store user data from an information device in order to increase the speed and/or the effective storage capacity of the data storage system. In some examples, a portion of a standard size block of user data can be stored on spaces of the non IC based memory that are deficient for storing a standard size block with the remaining portion being stored in IC based memory. Portions of a file of user data may be non-volatilely stored in the IC based memory in order to more quickly provide the file to an information device. For example, data of a file, that if stored in a location on the non IC based media would significantly increase the retrieval time of the file, can be stored in the IC based media.

Advanced RF enhancement-mode FETs with improved gate properties

Abstract: A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

Under bump metallurgy structural design for high reliability bumped packages

Abstract: A method for creating an under bump metallization layer ( 37 ) is provided. In accordance with the method, a die ( 33 ) is provided which has a die pad ( 35 ) disposed thereon. A photo-definable polymer ( 51 or 71 ) is deposited on the die pad, and an aperture ( 66 ) is created in the photo-definable polymer. Finally, an under bump metallization layer ( 37 ) is deposited in the aperture. A die package is also provided comprising a die having a die pad ( 35 ) disposed thereon, and having an under bump metallization layer ( 37 ) disposed on the die pad. The structure has a depression or receptacle ( 57 ) therein and has a thickness of at least about 20 microns.

Non-volatile memory device and method for forming

Abstract: In one embodiment, a semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into a semiconductor substrate (20), where a channel region (28) is located between a top surface of the substrate (20) and the highly doped layer (26). In an alternate embodiment, a semiconductor device (70) has a counterdoped channel (86) and an anti-punch through region (74) below the channel. A gate stack (32) is formed over the substrate (20). A source (52) and drain (54, 53) having a second conductivity type are implanted into the substrate. The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, a halo region (46), having the second conductivity type and implanted at an angle in the drain side, may be used to assist in hot carrier injection which allows a higher programming speed.

Flip-chip structure and method for high quality inductors and transformers

Abstract: A structure and method for achieving a flip-chip semiconductor device having plated copper inductors ( 4 ), transformers ( 16 ), interconnect, and power busing that is electrically superior, lower cost, and provides for higher quality inductors as well as lower losses for on-chip transformers. Providing a solder dam ( 8, 24, 28 ) enables the fabrication of flip-chip solder bumps directly on to inductors and transformers.

SOI polysilicon trench refill perimeter oxide anchor scheme

Abstract: A method for creating a MEMS structure is provided. In accordance with the method, a substrate (53) is provided having a sacrificial layer (55) disposed thereon and having a layer of silicon (57) disposed over the sacrificial layer. A first trench (59) is created which extends through the silica layer and the sacrificial layer and which separates the sacrificial layer into a first region (61) enclosed by the first trench and a second region (63) exterior to the first trench. A first material (65) is deposited into the first trench such that the first material fills the first trench to a depth at least equal to the thickness of the sacrificial layer. A second trench (71) is created exterior to the first trench which extends through at least the silicon layer and exposes at least a portion of the second region of the sacrificial layer. The second region of the sacrificial layer is contacted, by way of the second trench, with a chemical etching solution adapted to etch the sacrificial layer, said etching solution being selective to the first material.

Method of applying cladding material on conductive lines of MRAM devices

Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Data prefetching apparatus in a data processing system and method therefor

Abstract: A data processing system (20) is able to perform parameter-selectable prefetch instructions to prefetch data for a cache (38). When attempting to be backward compatible with previously written code, sometimes performing this instruction can result in attempting to prefetch redundant data by prefetching the same data twice. In order to prevent this, the parameters of the instruction are analyzed to determine if such redundant data will be prefetched. If so, then the parameters are altered to avoid prefetching redundant data. In some of the possibilities for the parameters of the instruction, the altering of the parameters requires significant circuitry so that an alternative approach is used. This alternative but slower approach, which can be used in the same system with the first approach, detects if the line of the cache that is currently being requested is the same as the previous request. If so, the current request is not executed.

Radio receiver having an adaptive equalizer and method therefor

Abstract: A radio receiver ( 100 ) has an equalizer ( 500 ) that operates in the time domain to remove residual interference that is not removed by an IF filter ( 200 ) operating in the frequency domain that is caused by an adjacent interfering FM station. The equalizer ( 500 ) includes a modified constant modulus algorithm (CMA) to generate a tap update signal from the output of the equalizer ( 500 ). The equalizer ( 500 ) uses the modified CMA to reduce an amplitude fluctuation of the received signal caused by the adjacent interfering station. The CMA is modified to use an infinite impulse response (IIR) filter ( 540 ) to generate the tap update. The IIR filter ( 540 ) also speeds up a convergence of the modified CMA to provide better performance.

Method and apparatus for generating a pulse width modulated signal

Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.