Showing papers by "Teradyne published in 1998"

Low cost, easy to use automatic test system software

Abstract: Automatic test equipment for semiconductor devices with low cost, easy to use software for developing and executing test programs. The tester is controlled with a computer work station running a commercially available spread sheet program. The commercially available spread sheet program is set as an application to provide a program development environment. In addition, programs made with the commercially available spread sheet program control the execution of tests on semiconductor devices. The tester is easy to program because use of the commercially available spread sheet program generates well known programming interfaces. In this way, the commercially available spread sheet program implements the software controlling the tester rather than merely providing spread sheet functions used by the application. The software controlling the automatic test equipment is therefore very easy to program or modify. It is also very easy to program.

Low cost, highly parallel memory tester

Abstract: Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port.

Robust, small scale electrical contactor

Abstract: A contactor for use in testing integrated circuit chips. The contactor is made with an array of V-shaped contact elements. The V-shaped contact elements are nested so that the contact elements can be longer than the pitch of the contact points. In this way, the compliance of the beam portions of the contact elements can be increased. Also, the V-shape is very robust. Further, the V-shape allows “fly-by” testing, which is very useful at high speeds.

Tester with fast refire recovery time

Abstract: Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signal are generated. Significant advantages in both cost and size are achieved by incorporating multiple channels on one integrated circuit chip. To allow this level of integration without degrading timing accuracy, a series of design techniques are employed. These techniques include the use of guard rings and guard layers, placement of circuit elements in relation to the guard rings and guard layers, separate signal traces for power and ground for each channel, and circuit designs that allow the voltage across a filter capacitor to define a correction signal. Another feature of the disclosed embodiment is a fine delay element design that can be controlled for delay variations and incorporates calibration features. A further disclosed feature is circuitry that allows the tester to have a short refire recovery time.

Compensating for the effects of round-trip delay in automatic test equipment

Abstract: Improved pin electronics for automatic test equipment are disclosed which compensates for the effects of round-trip delay on signals transmitted by the pin electronics and a circuit under test along the same transmission line The pin electronics includes a driver and comparator circuitry, both of which are coupled to a transmission line connecting the pin electronics to a node of the circuit under test Signals produced by the pin electronics and the circuit under test are combined at the pin electronics due to the effects of round-trip delay between the pin electronics and the circuit under test The comparator circuitry takes a scaled version of the signal produced by the pin electronics and subtracts it from the combined signal, thereby recovering the signal produced by the circuit under test Other pin electronics are also disclosed that uses the scaled signal for modifying threshold voltages provided to the comparator circuitry, thereby facilitating measurement of the combined signal

Low cost memory tester with high throughput

Abstract: An automatic test system for testing semiconductor devices, particularly memory devices. The test system includes a handling device with several temperature controlled chambers, each associated with a test head. Trays of devices are loaded into the handling device and are brought to thermal equilibrium in each chamber before being tested. The number of test sites within each chamber is varied in inverse proportion to the time it takes to test a device at the temperature within the chamber.

Automated microwave test system with improved accuracy

Abstract: An automatic test system for microwave components. The test system includes internally switchable calibration references. As part of a calibration routine, incident power from a source is measured. During the measurement, calibration references are switched to change the amount of power reflected back to the source. Changes in the incident power measured continuously while this change occurs. The resulting measurements allow the source match term to be determined. Correction is made to the source amplitude to adjust for the source match.

Test system for integrated circuits using a single memory for both the parallel and scan modes of testing

Abstract: A semiconductor test system has a scan test mode and a parallel test mode. A single memory using substantially all of its storage space stores a) parallel test vectors for use during the parallel test mode, and b) parallel test vectors and scan test vectors for use during the scan test mode. A switch is used to change from the parallel test mode to the scan test mode. A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode. The speed of the scan test mode is increased by interleaving the memory and reading test vectors out of the memory in parallel. Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT). Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.

High performance probe interface for automatic test equipment

Abstract: A probe interface device is disclosed that includes a plurality of coaxial contact probe assemblies disposed in an insulative base. Each coaxial contact probe assembly includes a solid tubular shield with a coaxial signal contact probe, which is isolated from the shield by an insulative retainer; and, a solid tubular reference with another coaxial contact probe. The shield and the reference are soldered together at their respective ends. Further, the insulative base includes an upper retainer and a lower retainer attached to a hollow frame. The upper and lower retainers are provided with the same number of holes for engaging a plurality of coaxial contact probe assemblies. The probe interface device can be used for testing mixed-signal devices and is easy to manufacture.

Integrated multi-channel analog test instrument architecture providing flexible triggering

Abstract: Analog test instrument architecture for performing functional testing of electronic circuit assemblies is disclosed. The analog test instrument includes a plurality of identical channels, each channel including circuitry for driving test stimuli and measuring responses at one node of a circuit assembly under test. The driver and measurement circuitry in each channel implement functions that traditionally have been implemented in a test system using discrete instruments. The analog test instrument further includes a master clock reference, which is used for synchronizing the operation of the driver and measurement circuits. Each channel further includes triggering circuitry for distributing trigger events within the channel and to the other channels; and, an input buffer, which is shared by the measurement circuits in the channel. The synchronized operation, distributed trigger events, and shared input buffers are used to improve the correlation of measurements made during functional testing.

System for storing and searching named device parameter data in a test system for testing an integrated circuit

Abstract: This invention relates to automatic test equipment used in the manufacture of semiconductors and to the storage and searching of the named device parameter data used in the testing. A spreadsheet workbook has one or more spreadsheets containing nested levels of named device parameter data. A data manager stores the named data in a memory and searches for the stored named data when appropriate. The data manager has one or more containers each having a mode for storing nested levels of the named data in the form of a binary tree, and also in an ordered sequence vector. The data in the tree is mapped into the ordered sequence vector with numerical indicia defining the position of the named data in the ordered sequence vector. The containers are nested the same as the nested levels of the named data. Each container has a search mode which searches the tree for the named data and uses the mapping indicia associated with the named data to find the named data in the ordered sequence vector. The container then stores the numerical indicia. This search finds the named data and its order in the nested levels.

Heat-transfer enhancing features for semiconductor carriers and devices

Abstract: Convective heat transfer enhancement features are formed in trays for carrying and thermally conditioning semiconductor devices or on integrated circuit chip packages. Upward extending ribs, perpendicular to a fluid flow, are formed in the trays and/or packages for increasing the mixing of the fluid flow near the devices under test, thereby enhancing convective heat transfer to or from the devices. Downward extending ribs are also formed in the trays and/or packages. The upward and downward extending ribs formed in the trays are in a staggered relationship for facilitating the stacking of trays. Alternatively, a surface roughness is applied to the trays and/or packages. The surface roughness applied to the packages is such that sufficient smooth regions remain on the packages for allowing pick-and-place machines to handle the packages.

Testing the design: the evolution of test simulation

Abstract: In work done in cooperation with Texas Instruments, Analogy, and Teradyne it has been demonstrated that a simulation of a complete test system when combined with design models of an integrated circuit can reduce the cycle time required to get a new product to market. This paper will describe the development of such a system, its inclusion in the design flow for new IC development, and the resulting improvements in new product introduction from the viewpoint of design and test.

Production interface for an integrated circuit test system

Abstract: A production operator interface is created using self-contained ActiveX controls each of which provide an interface to a specific part of the overall test system. These controls all communicate among themselves automatically. The production interface uses an ActiveX "tester control" which provides an application programming interface to the rest of the software control system. A library of self-contained ActiveX controls is provided which contains "operator controls" which may be "dragged and dropped" into an operator window to provide the operator with information and the ability to control the test system. In addition a semiconductor test system needs to be adapted to work with one or more different packaged device handlers or wafer probers which position a semiconductor device for testing by the tester. An ActiveX operator control allows an operator to select a handler driver from a library of handler drivers.

Relayless voltage measurement in automatic test equipment

Abstract: A tester that is capable of performing voltage measurements on electronic circuits is disclosed. The tester includes voltage measurement circuitry with an input, a plurality of gain stages, and switching circuitry coupled between the input and the gain stages. The switching circuitry includes a plurality of diodes, and a portion of the gain stages includes current-to-voltage converters. Each diode is coupled to a respective current-to-voltage converter. By applying different bias voltages to the respective current-to-voltage converters, the diodes can be made to conduct current for different ranges of voltages at the input. The output of each current-to-voltage converter is proportional to a respective voltage range.

The CAT-exact data transfer to DDS-generated clock domains in a single-chip modular solution

Abstract: Mixed-signal testing requires exact synchronization between digital and analog clock domains. A unique ASIC, the CAT, has been developed to automate the vector handoff for analog instrument control and synchronization, while producing arbitrary precision analog clocks.

Steganography using the minimax eigenvalue decomposition

Abstract: This paper presents result of applying the minimax eigenvalue decomposition (MED), a morphology type transform, that hides data within digital images as part of a flexible, computationally robust algorithm. This new algorithm presents a general method for hiding information within an image, although the strength of this algorithm lies in authentication. Authentication is the establishment of ownership of digital information, and is a type of watermarking. While no self-authenticating techniques are currently known, the algorithm presented here provides a certain level of self-authentication regardless of the particular information embedded in the data. The algorithm is applied to ten different images acquired over the internet, three of which are included in this document. Information in the form of a binary bit stream is inserted into each image data. A measure is created to determine how close an image containing message data is to its original image. A visual comparison is also performed. Keys, or information separate from the message data that is generated by the embedding techniques, are used to establish authenticity of the image data. This is different from most current steganography techniques that rely on embedded data integrity to establish authenticity. An analysis of the results is presented.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Adjustable tooling pin

Abstract: A tooling pin assembly used with a receiver in a printed circuit board tester is disclosed. The tooling pin assembly includes a locating pin with a core threaded to receive a screw, and a bushing for supporting and guiding the locating pin relative to the receiver. When the screw is rotated in one direction, the locating pin moves out of the bushing and passes through a hole in the receiver for engaging a test fixture. When the screw is rotated in the opposite direction, the locating pin retracts into the bushing until it is below the plane of the receiver. The ability to extend and retract the locating pin is especially useful when the tooling pin assembly is used with a receiver designed to hold test fixtures of various sizes.

Automatic test equipment for semiconductor device

Abstract: Automatic lest equipment for testing semiconductor devices equipment includes a) a clock; b) a delay line comprised of a plurality of delay stages (212), each delay stage (212) having an input and an output and a control input, with the input of the first delay stage (212(0)) coupled to the clock and the input of every other delay stage coupled to the output of the preceding stage in the delay line; said automatic test equipment characterised by: c) a phase detector (214) having a first input coupled to an output of a delay stage in the delay line and in an input coupled to the output of a prior delay stage in the delay line; and d) a control circuit (216) having an input coupled to the output of the phase detector and an output connected to the control inputs of each of the delay stages in the delay line.

The World Wide Web leads a revolution in ATE programming environments

Abstract: New software technologies, including the World Wide Web, may seem far removed from the tasks facing test program set (TPS) developers, but they promise to revolutionize the way TPS data is organized, presented, and used. This paper will describe how an integrated TPS development and execution environment can capitalize on these new technologies to improve test programming efficiency.

Advantages of digital convergence for functional test

Abstract: With the ever-increasing complexity and clock rates of today's weapon system electronics, digital functional test plays a critical role in depot test. This is likely to become even more so over the next in years as the next generation of weapon systems are deployed. At the same time that system complexity is increasing, the number of joint weapon system programs is growing. JSF and V-22 are just two high-profile examples. DoD initiatives like CIWG, Critical Interfaces Working Group, are driving toward a common test environment as a way to reduce the costs of TPS development and test systems. For complex joint programs, a common environment is widely viewed as an essential factor in minimizing the overall cost of test. In many ways, the DoD has succeeded in establishing a common test environment for digital test through digital test convergence. This paper discusses the parameters that define commonality and the implementation trade-offs.

Simplifying TPS development and execution using a PC, Web-based environment

Abstract: Test Program Set (TPS) development and test execution for modern electronic modules involves the integration of a myriad of software and hardware tools which are inherently difficult to integrate. It is not uncommon to have a combination of digital, analog, and mixed-signal test routines in the same test program, all of which use different tools for development and execution. While data exchange and software language standards have helped provide a common ground for reducing the barriers to integration, there has been no progress in providing a user environment that can leverage these advances. This paper describes a PC-based TPS development, documentation, and execution environment that uses Microsoft COM interfaces, high-level scripting and World Wide Web technologies to integrate development processes and point tools from multiple sources. The result is an open, easily reconfigurable TPS operating environment that uniquely combines flexibility with a process-oriented framework.

Semiconductor tester with data serializer

Abstract: A semiconductor tester with features to facilitate testing of embedded memories. The circuitry allows tests to be generated algorithmically, but can be used in conjunction with scan test structures of semiconductor devices. Programming and debug time can be significantly reduced. The tester includes an algorithmic pattern generator that can generate a pattern for testing a memory. The tester also includes serializer circuits coupled to the algorithmic pattern generators that can convert the test pattern generated by the algorithmic pattern generator into one or more serial bit streams useful for scan testing an embedded memory.

Timing generator with fast refire recovery time

Abstract: Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signal are generated. Significant advantages in both cost and size are achieved by incorporating multiple channels on one integrated circuit chip. To allow this level of integration without degrading timing accuracy, a series of design techniques are employed. These techniques include the use of guard rings and guard layers, placement of circuit elements in relation to the guard rings and guard layers, separate signal traces for power and ground for each channel, and circuit designs that allow the voltage across a filter capacitor to define a correction signal. Another feature of the disclosed embodiment is a fine delay element design that can be controlled for delay variations and incorporates calibration features. A further disclosed feature is circuitry that allows the tester to have a short refire recovery time.

High quality, easy to use, on time ATE software...Can it be done?

Abstract: ATE software is highly complex and historically has been created from scratch by ATE vendors. This technique has often led to software of poor quality which is difficult to learn and use, and to uncertain delivery schedules. This paper outlines an alternative technique of creating ATE software using commercially available software components as building blocks. This results in higher quality, reduced development time, reliable schedules, and an end product that is easier to lean and use.