Showing papers in "IEEE Transactions on Circuits and Systems in 2004"

A recurrent neural network for nonlinear convex optimization subject to nonlinear inequality constraints

Abstract: This paper presents a novel recurrent neural network for solving nonlinear convex programming problems subject to nonlinear inequality constraints. Under the condition that the objective function is convex and all constraint functions are strictly convex or that the objective function is strictly convex and the constraint function is convex, the proposed neural network is proved to be stable in the sense of Lyapunov and globally convergent to an exact optimal solution. Compared with the existing neural networks for solving such nonlinear optimization problems, the proposed neural network has two major advantages. One is that it can solve convex programming problems with general convex inequality constraints. Another is that it does not require a Lipschitz condition on the objective function and constraint function. Simulation results are given to illustrate further the global convergence and performance of the proposed neural network for constrained nonlinear optimization.

High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications

Abstract: High-speed high-resolution analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR). However, lowering the OSR limits the efficiency of a ADC in achieving a high-resolution A/D conversion. This paper presents several techniques that enable the OSR reduction in ADCs without compromising the resolution. 1) Noise transfer function (NTF). In this paper, a single-stage multibit modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs. Its key fea- tures include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities. Its performance is validated through behavioral simulations and compared to traditional mod- ulator structures. 2) Signal transfer function (STF). This paper describes how the STF of a modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation. 3) Dynamic element matching (DEM) is also presented. Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit modulator, especially when the number of DAC elements is large. However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range. This paper proposes a simple technique, called Pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio. Its implementation adds no extra delay in the feedback loop and requires only minimal additional digital hardware. Existing schemes for DWA tone reduction are also compared.

Modified register-exchange Viterbi decoder for low-power wireless communications

Abstract: In this paper, a new implementation of the Viterbi decoder (VD), based on a modified register-exchange (RE) method, is proposed. Conceptually, the RE method is simpler and faster than the trace-back (TB) method. However, the disadvantage of the RE method is that every bit in the memory must be read and rewritten for each bit of information decoded. The proposed implementation adopts the "pointer" concept: a pointer is assigned to each register. Instead of copying the contents of one register to another, the pointer which points to the first register is altered to point to the second register. Power-dissipation, performance, memory size, and the speed of the survivor sequence management are analyzed for both the TB method, and the proposed RE method. The analysis indicates an average power reduction of 23% for the new VD, compared to the power dissipation of the VD described in the literature for the third generation of wireless applications. The bit-error rate is 10/sup -5/ with a signal-to-noise ratio of approximately 6.3 dB for a continuous, uncontrolled encoded sequence. Moreover, the memory requirements of the new implementation are reduced by half. All the read and write operations in the survivor sequence management are executed at the data rate frequency which increases the maximum frequency.

Design of low-voltage MOSFET-only ΣΔ modulators in standard digital CMOS technology.

Abstract: A design strategy of low-voltage high-linearity MOSFET-only /spl Sigma//spl Delta/ modulators in standard digital CMOS technology is presented. The modulators use substrate-biased MOSFETs in the depletion region as capacitors, linearized by different compensation techniques. This work shows the design, simulation and measured results of a number of MOSFET-only /spl Sigma//spl Delta/ modulators using different implementations of so called compensated depletion-mode MOS capacitors. The modulators are designed for the demands of speech band applications. The performance of the modulators proves the capability of compensated depletion-mode MOS capacitors to fulfill analog circuit requirements at low supply voltages with reduced processing efforts.

One-tap wideband I/Q compensation for zero-IF filters

Abstract: The I/Q imbalance is one of the performance bottlenecks in transceivers with stringent requirements imposed by applications such as 80211a The mismatch between the frequency responses of two analog low-pass filters, used, eg, for channel selection in zero-IF receivers, makes this I/Q imbalance frequency dependent Usually, frequency-dependent I/Q mismatch is estimated and corrected by adaptive techniques, which are complex to implement and may converge slowly due to noise In this work, a simple, delay-based I/Q compensation scheme is proposed based on an extensive statistical analysis Its digital implementation uses only two coefficients, which are tuned by a one-step two-tone error estimation Simulations show that this hardware-efficient scheme significantly reduces the I/Q imbalance

The tiling phenomenon in ΣΔ modulation.

Abstract: The theoretical error signal analysis of a sigma–delta ( ) modulator is a difficult problem due to the presence of a nonlinear operation (the amplitude quantization) in a feedback loop. In this paper, new deterministic knowledge on the transfer function of a modulator is established, thanks to some recently observed properties of its state variables. For a large class of typical modulators with constant inputs, the state variables appear to remain in a tile. We show what characteristics in a modulator are specifically responsible for this property and give some initial proof of it. Under a constant input, the tiling phenomenon has as fundamental consequence that the output is a fixed and memoryless modulo function of successive integrated versions of the input. This gives the theoretical knowledge that the modulator has an equivalent feedforward circuit expression. We give some immediate theoretical consequences on error analysis including the case of time-varying inputs.

Spatial Pattern Formation via Reaction-Diffusion Dynamics in 32 32 4 CNN Chip

Abstract: Reaction-diffusion dynamics have been proposed to explain pattern-formation behavior in a variety of systems, e.g., chemical and biological. This paper describes a cellular neural network chip that exhibits spatially organized patterns of activity, which are formed by reaction diffusion. The chip contains four 32 32 cell arrays of transistors which are locally coupled and operate in weak inversion. Typical patterns consist of alternating regions of high- and low-drain currents with a preferred width, but no preferred orientation. Experimental, theoretical, and simulation results for this chip are in complete concordance, demonstrating that conventional very large-scale integration tech- nology can be an ideal substrate for studying the spatio-temporal dynamics and applications of reaction-diffusion. The chip, which was fabricated in a 0.5- m process, settles to steady-state patterns within several hundred microseconds and dissipates 10.55 mW. Index Terms—Analog very large-scale integration (VLSI), cel- lular neural network (CNN), CMOS, nonlinear circuits, nonlinear dynamics, pattern formation, reaction diffusion, Turing pattern, VLSI.

Self-tuning algorithms for high-performance bandpass switched-capacitor ΣΔ modulators.

Abstract: Switched-capacitor high-frequency bandpass /spl Sigma//spl Delta/ modulators could suffer from capacitor mismatch, finite opamp dc gain, and finite opamp bandwidth. These problems make the notch frequency and the quality factor of the zeros of the noise transfer function to deviate from their nominal values, strongly affecting the modulator dynamic range (DR). In order to avoid this situation, two sampled-data algorithms have been developed which allow to self-calibrate the bandpass /spl Sigma//spl Delta/ modulators. They use 3500 gate and 0.043 mm/sup 2/ area and consume power only when they are active, while, when the system is on, they are off and do not interfere with standard operation. The validity of the proposal is demonstrated by a silicon prototype in which the proposed solution allows to guarantee a 75-dB DR performance also under worst case conditions. In the particular case, it allows for the recovery of 3 dB in the SNR for the 200-kHz FM band (from 73 to 76 dB).

Numerical method for determining the quantization error PDF of single-bit ΣΔ Modulators.

Abstract: Existing models for the quantizer of modula- tors make assumptions on the probability density function (pdf) of the quantization error, or some other convenient signal of the modulator. In this paper, a method for the determination of this pdf for single-bit modulators is presented. First, a numerical method is proposed in order to solve the simplified equation for the quantization error pdf for first-order systems considering noiseless and noisy dc input signals. Then, it is shown how most practical high-order modulators, resulting from well-established design methods, can be modeled as first-order systems plus an ad- ditive noise source at the input. Hence, their quantization error pdf is analyzed using the proposed method. Simulation results are shown to be in considerable agreement with those of the proposed method.