Showing papers in "Integration in 2022"

A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications

Abstract: This paper presents a novel dual mode configurable and tunable power amplifier (PA) that achieves a wide-bandwidth and high gain across a operational frequency spectrum of 20 to 30 GHz. The proposed PA used two-stage tunable PA which can be configured as a tunable synchronous mode or tunable stagger-tuned mode PA. PA is implemented by using a distortion-free varactor at the input and output tank of PA. The designed PA includes a high-Q CMOS active inductor (CAI) which provides a widely tunable output matching network. The resistive feedback is used for self-biasing in the designed PA which helps to enhance the linearity, stability of common source (CS) amplifier. The inter-stage impedance matching network consists of shunt and series resonance circuits are employed for maximum power added efficiency (PAE). Furthermore, the capacitive coupled reuse technique is implemented in each stage between the cascaded transistor to reduce the power consumption. A proposed PA is designed using a 65 nm CMOS technology. A measured power gain at the synchronous operation of PA is 28.4 ±0.5 dB with 1.31 GHz bandwidth while power gain at staggered operation is 22.1 ±0.5 dB with 3.71 GHz bandwidth. The measured saturated power (Psat) is 14.21 dBm and the noise figure (NF) is 5.2 dB. The group delay (GD) variation for staggered operation is 57 ±10 ps from 20-30 GHz. A proposed PA exhibits good linearity (IIP3) of 14.5 dBm and PAE is 47.5 % at 24 GHz. The power consumption of a designed PA is 48.56 mW with a supply voltage of 1.2 V.

A new adaptive selection strategy for reducing latency in networks on chip

Abstract: Networks on chips (NoCs) are a concept inspired by computer networks for constructing multiprocessor systems that can handle communication across processing cores. One of the most critical applications of NOC is efficient nonstop routing. Different routes exist in these networks to get from one node to another; thus, a function that can assist in determining the optimum route to the target should be available. This paper uses a new hybrid method called Scored Regional congestion aware and DICA (ScRD) to select a better output channel and increase NOC performance. After applying the ScRD algorithm, the traffic packets are examined by an analyzer, which determines if the NoC traffic is local or non-local based on the number of hops. Therefore, if the traffic is local, a scoring mechanism will select a better output channel; otherwise, the best output channel will be chosen using DICA or RCA selection functions, depending on the system state and the introduced parameter. Finally, Nirgam simulation was used to test the suggested method under various traffic conditions and selection criteria. The simulation results demonstrated that the strategy outperformed delay time, throughput, and energy consumption alternatives. It reduced packet delay by 27.10% and increased throughput by 10%. When these two factors were considered, energy consumption dropped by 6.86%. Also, the synthesis results showed that the hardware cost of the proposed approach is 1.2% lower than the two basic methods.

High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding

Abstract: Nowadays, secure digital data in store and transmission is an important issue. Cryptographic methods are widely used to provide optimal security for multimedia data. In this paper, a good performance implementation of a strong block-cipher system is proposed. This article's contribution is to develop a new method to block-cipher hardware system based on DNA biological properties and various 3D chaotic maps. In this scheme, the high-level security is achieved by chaotic sequences generated by a robust chaos-based PRNG based on the Lorenz, Chua, Rossler, and Chen chaotic maps. The latter is used to generates high-quality keys that are applied for encryption. Thus, a high-security block cipher approach for encrypting and decrypting images has been developed. To increase the confusion process complexity, several biological operations, such as DNA-XOR, are added to the encryption process. Furthermore, a novel hardware architecture of the proposed block-cipher system is put forward. The latter achieves a low power consumption, good frequency of 192.813 MHz and high throughput of 24,576,153 Mbps built. The security analysis demonstrates that the cryptosystem provides effective security. The proposed PRNG validated successfully both the NIST SP 800–22 test suite and the U01-Test. Various tests are performed, such as statical tests, phase analysis and differential attacks applied to different images. A comparison of the proposed algorithm with several newly developed encryption algorithms demonstrates that our system generates good results.

Agile-AES: Implementation of configurable AES primitive with agile design approach

Abstract: In the data-centric era, interconnected devices must be able to communicate efficiently and securely with their hosts even over untrusted networks. This led to the adoption of several end-to-end security protocols that employ various efficient and elegant encryption algorithms, such as Advanced Encryption Standard (AES), often implemented with hardware modules since there is usually no good solution to install security software on the device itself. State-of-the-art AES hardware implementations typically focus on optimizing a single metric, e.g. throughput or area, and are tedious to adapt to a wider set of design constraints. Applying an agile approach to hardware development is increasingly important, and this is especially critical for hardware security primitives that need to be consumed in various systems. In this work, we develop Agile-AES, an open-source, flexible, parameterizable, hardware implementation of AES, combining many best-known practices. The agile and feature-rich implementation was based on the Chisel framework, through which flexibility is instrumented to support various key length, topology, mode of operation, local memory type, S-box fabric, side-channel attack defense techniques, and interfaces. Despite covering a larger design space, our proposed implementation has 50% fewer lines of code compared to existing Verilog versions — a crucial advantage in terms of maintainability and development productivity. To evaluate the QoR out of this implementation approach, we pick representative configurations and evaluate utilization, power and throughput on both entry level and server-grade FPGAs and compare against the Verilog and HLS counterpart implementations. It shows very comparable results to the Verilog implementation and better QoR compared to the HLS-based implementation.

Application driven routing for mesh based Network-on-Chip architectures

Abstract: Expertise and intuition of chip design engineers supplemented by a unique design objective governs the choice of routing algorithm in Network-on-Chip(NoC) based systems. However, the same choices when considered for more than one performance parameter of the network, do not yield expected results since different applications exhibit different network performances for the same routing technique. Thus, we advocate use of an application pattern driven routing approach instead of the usual static routing strategies. In this paper, we propose an application pattern driven dynamic routing approach for NoC based systems while committed to optimize desired performance parameters. Our proposed methodology serves a dual purpose of improving the network performance of the NoC based system as well as relieving the design engineers from making the complex and tedious routing decisions. A machine learning based predictive approach is employed in our approach to classifying traffic patterns and it achieves 94.78 % accuracy while our overall proposed methodology achieves significant improvement in power consumption and throughput as compared to state of art works available in literature.

Design automation for continuous-flow microfluidic biochips: A comprehensive review

Abstract: Continuous-flow microfluidic biochips (CFMBs), also known as lab-on-a-chip platforms, have attracted considerable attentions in the past two decades and have been widely used in various laboratory procedures in biomedicine and biochemistry such as point-of-care diagnosis and protein crystallization. Besides a completely automatic execution procedure, these micrometerscale devices offer several advantages over the conventional fluidic platforms, e.g., low sample/reagent consumption, low manufacturing cost, and high execution efficiency. However, similar to the early development of integrated circuits, as the feature size of biochips keeps shrinking, tens of thousands microvalves can now be integrated into a single chip. Consequently, traditional manual-based chip design is no longer suitable and Computer-aided Design (CAD) tools have to be introduced to deal with the large-scale integration of such chips. This paper presents a comprehensive review of recent advances in the design automation of CFMBs, including CAD techniques for architecture synthesis, volume assignment and sample preparation, testing, fault-tolerant design, and washing. These tools have great significance in advancing the automation level of biochip design and further promote their wide adoption. Finally, future trends and potential research topics are discussed in detail to further improve the performance of CFMBs.

Multi-source data fusion technique for parametric fault diagnosis in analog circuits

Abstract: Input test signal plays important role in testing of analog circuits. Single type of input stimulus cannot maximally reveal the state of the circuit. To combat this shortcoming, this work proposes to integrate information from the output responses corresponding to different input stimuli and to use the combined information to improve the accuracy of fault diagnosis in analog circuits. The circuit under test is excited with different input signals and wavelet features are extracted from the output responses of the circuit. Ultimate fault features have been defined by applying data fusion algorithm to the sets of wavelet features obtained from individual output. Data fusion has been performed in two steps, data whitening and Principal component analysis (PCA). Fused features are used to train SVM (Support Vector Machine) classifier for fault diagnosis. The proposed approach is validated with three types of filter circuits, i.e. Sallen-Key band pass filter, four OPAMP high pass filter and elliptic low pass filter. The average accuracy of the proposed fault classification method has been found greater than 99.8% for all the test circuits. The proposed technique offers improved classification accuracy, lower computational burden and lesser implementation complexity.

An effective watermarking technique using BTC and SVD for image authentication and quality recovery

Abstract: Digital image protection has become a major concern in digital communication. Watermarking digital images has long been thought to be a good way to ensure the image quality. This paper proposes a watermarking scheme for image authentication and recovery of tampered images based on block truncation coding (BTC) and singular value decomposition (SVD). Here the image is divided into 4x4 non-overlapping blocks. Then the watermark information for authentication and recovery is embedded into it. The authentication watermark for each block will be generated using SVD and XOR operation, then it gets embedded into it. Simultaneously, the recovery watermark of each block will be generated using BTC and gets embedded in a mapped block. The watermark information gets embedded in two least significant bits (LSBs) of each pixel in a block. The proposed scheme got a higher degree of watermarking with better recovery against various kinds of attacks.

A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*

Abstract: A novel symmetrical four-wing fourth-order chaotic system is constructed. The basic dynamic characteristics of the system were analyzed by phase diagram, bifurcation diagram, Lyapunov index spectrum, Poincare cross section diagram and 0–1 test. In addition, the chaotic attractors under different parameters in the system are analyzed. In the dynamic analysis of the new system, it is found that the new system has some characteristics, such as multi-stability, offset boosting, multi-state transition phenomenon, transient chaos and intermittent chaos, and coexistence of multiple attractors. These features have the value of in-depth analysis compared to previous systems and can make it promising for more applications. Moreover, after calculating the complexity of the system by C0 algorithm at different initial values, it is found that the complexity of the system has been stable. Due to the existence of many characteristics, the new chaotic system has attracted great attention. At the same time, the circuit design of the system is realized by using Multisim simulation software and FPGA digital hardware circuit. Finally, a novel and efficient image encryption algorithm is designed by combining multi-direction pixel scrambling and DNA dynamic encryption. The NIST test, key space, encryption histogram, adjacent pixel correlation, robustness and information entropy are analyzed by encrypting images using chaotic sequences of the new system. In a word, its plentiful characteristics and intricate phenomena have significant reference value in the field of chaotic image encryption.

A memristive chaotic system with rich dynamical behavior and circuit implementation

Abstract: In this paper, a novel four-dimensional autonomous chaotic system based on memristive diode bridge is presented, and it consists of a simple linear oscillation and a memristor. According to the mathematical model of the system, the equilibrium point is analyzed, and the phase portraits, time-domain sequences, bifurcation diagrams and Lyapunov exponent spectrums are numerically simulated. The rich dynamical behavior of proposed system is investigated. It includes multistability, offset boosting and chaotic bursting. In addition, the circuit simulation and Field-Programmable Gate Array (FPGA) hardware experiment are carried out to verify the feasibility of the system. Then the application of proposed system in chaotic image encryption is presented. By carrying out some security performance analyses, we show that the proposed system has good security performance.

Low power chaotic oscillator employing CMOS

Abstract: A CMOS based simple chaotic oscillator is designed by using three grounded capacitors, six transistors and an external comparator sub-circuit as a signum nonlinearity function in a feedback loop. The proposed system has been modeled in terms of three ODEs without multiplication terms and shows a unique, surprising behavior across stable and unstable equilibrium points. Numerical analysis of the proposed chaotic model generates possible dynamical characteristics in terms of bifurcation diagram, equilibrium points stability, Lyapunov exponents and basin attractor. The proposed design includes 0.18 μ m CMOS parameter for the verification of electronic circuits. Both numerical and circuit simulation results have similar behavior that validates the workability of the proposed chaotic signal generator. The significant contribution of the proposed chaotic oscillator offers less design complexity, a relatively more minor number of MOS transistors, free from multiplication term, resistor and inductor with a grounded capacitor. Moreover, it exhibits low power consumption (16 nW) and a broad frequency operation spectra. • We introduced a CMOS based simple chaotic oscillator design by using MOS transistors and an external comparator sub-circuit in a feedback loop. • Numerical analysis of the proposed chaotic model generates all possible dynamical characteristics. • The proposed design includes 0.18 μ m CMOS parameter for the verification of electronic circuits. • The significant contribution of the proposed chaotic oscillator offers less design complexity and components.

WDP-BNN: Efficient wafer defect pattern classification via binarized neural network

Abstract: Wafer map defect pattern classification using convolutional neural network (CNN) has gained a lot of attention in recent years but it demands huge computation and memory cost. Therefore, a WDP-BNN framework based on the binarized neural network is proposed to reduce memory requirement by 29.70× and speed up by 1.66×. To overcome the imbalance problem and performance loss due to binarization of network, advanced data augmentation methods including (Chip Reverse, Chip Translate, Chip Combine) along with random under-sampling method have incorporated in the framework. Experimental results on the WM-811K dataset have demonstrated that the WDP-BNN model has outperformed the state-of-the-art works with the highest classification accuracy of 94.83% and the memory reduction of 1.10-25.93×.

Design of hyperchaotic system based on multi-scroll and its encryption algorithm in color image

Abstract: Chaotic systems are suitable for image encryption due to their numerous intrinsic properties. However, the low-dimensional chaotic systems used in many existing chaos-based image encryption algorithms suffer from various drawbacks. To overcome such problems, a new four-dimensional multi-scroll hyperchaotic system is constructed in this paper. By studying the stability of equilibrium point, dissipation attractors, Lyapunov exponent spectrum, and bifurcation diagram of the system, these are proved that the system has rich dynamical behaviors. Then, based on the system, a new color image encryption algorithm is designed by using the classical structure of the ‘scrambling-diffusion-scrambling’ algorithm. In this image encryption algorithm, an optimized Arnold transform is used and the plaintext pixel sum is applied to the scrambling parameters so that different plaintext image pixels correspond to different scrambling parameters and are fully resistant to plaintext attacks. Then for the three Red, Green, Blue (RGB) channels, three different diffusion directions are adopted. Finally, the correlation between the pixels is further broken by an ascending permutation scrambling operation to get the final encrypted image. The experimental results show that the key space is up to 2207, the information entropy is up to 7.9998, the Number of Pixels Change Rate (NPCR) and the Unified Average Changing Intensity (UACI) values are close to the ideal values, the scheme can resist exhaustive and differential attacks, and the scheme has good robustness through noise attacks and crop attacks.

Machine learning classification algorithm for VLSI test cost reduction

Abstract: Testing of Integrated Circuits (ICs) is essential for weeding out defects before the products are shipped to customers. With the growing complexity of ICs, high-cost specification tests are becoming a bottleneck owing to their lengthy Test Time (TT). TT becomes particularly critical when the overall costs of ICs have to be taken into consideration. Considering the problem that TT takes too long in the traditional test, i.e., a test with full Test Patterns (TPs), this paper proposes an improved K-Nearest Neighbor (KNN) algorithm to classify the defects, i.e., this TP selection approach utilizes a classification model to select the valid patterns only, to shorten the TT. Experimental results demonstrate that compared with the traditional method, the proposed method successfully reduces the TT by 1.75 times. Furthermore, the experimental results represent the optimal compromise between TC and Test Quality (TQ).

Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective

Abstract: In the past decade, monolithic three dimensional integrated circuits (M3D-ICs) advance fast and demonstrate several important breakthroughs in the fabrication process and circuit level design. This article surveys recent research works on M3D technology from the computer system perspective with several case studies, and presents the opportunities as well as the challenges brought by this emerging technology. We also discuss possible applications of M3D based computer architectures. As the M3D technology is attracting enormous attention from both industry and academia, we expect that this article can be a good reference for the researchers and industrial partners who are interested in this fast evolving field, and promote the research activities of computer system/architecture design with this emerging technology.

A new low-power Dynamic-GDI full adder in CNFET technology

Abstract: In this paper, a new low-power full-adder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the proposed approach, the basic logic circuits such as XOR and XNOR gates are implemented which results in a full-swing, full-adder cell in the CNFET technology. The proposed circuit is simulated in HSPICE using CNFET model parameters. Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder circuit.

DULBC: A dynamic ultra-lightweight block cipher with high-throughput

Abstract: Lightweight block ciphers are important for implementing security services on constrained devices today. In this paper, we propose a novel ultra-lightweight block cipher DULBC based on a dynamic SPN structure. The round function of DULBC adopts an unfixed F-function and a bit-based permutation. The choice of the F-function depends on 2 bits of the round keys. This means the encryption process of the cipher is uncertain and its security is greatly improved. Also, a strong 4 × 4 S-box with fewer logic gates is proposed, which costs low hardware resources and ensures excellent performances. We have conducted FPGA implementation and ASIC implementation on DULBC. The throughput of DULBC-80/128 is 555.03/443.84 Mbps and the area of the 16-bit serial architecture of DULBC-80/128 is 1075/1351 GEs, respectively. DULBC is secure and efficient according to our experiments and comparisons. • A novel lightweight block cipher with dynamic structure to improve security and privacy. • Performance of the 4 × 4 S-box with fewer logic gates is even better compared with the isomorphic S-boxes. • High throughput and low area consumption in hardware implementation.

A new 4D Memristor chaotic system: Analysis and implementation

Abstract: In this paper, a new chaotic memristor system is developed based on a well-known nonlinear circuit. By replacing the nonlinear positive conductance of Shinriki's circuit with a memristor emulator, the new simple chaotic circuit can reduce the number of active elements and reduce power consumption. An analysis of equilibria and stability, dissipative properties, Lyapunov exponents, Kaplan-Yorke dimensions, and bifurcation diagrams is presented as well as numerical simulation of the new memristor chaotic system. As a final step, the electronic circuit is designed using Multisim software, which is complemented by a physical realization to demonstrate the feasibility of the chaotic system. • A new chaotic memristor system based on a well-known nonlinear circuit is proposed. • The new memristor has the advantage of reducing the number of active elements and reducing power consumption accordingly. • The proposed chaotic system is studied by analyzing its equilibrium and stability, dissipative properties, Lyapunov exponents, Kaplan-Yorke dimension, and bifurcations diagrams. • Multisim software is used to design the electronic circuit, while a physical realization is provided to demonstrate the system's feasibility.

Low power, high speed approximate multiplier for error resilient applications

Abstract: This paper proposes novel constant carry-based approximate compressors for partial product reduction in the binary multiplier. The constant carry compressors have only Sum as output and the output carry bits are either constant 0 or 1 and hence no requirement of logic computation. This will evidently remove the carry chain when these compressors are utilized for column reduction in multipliers. This work examined the 4-bit multiplier with two different constant carry chains (Type-1, Type-2) since there is possibility of two constants. The 8-bit multipliers are built using 4-bit recursively with both the types. By analyzing the two modes, it is concluded that Type-1 i.e., constant carry chain of all zeros is efficient in terms of error and energy. The existing best design of approximate compressor based multipliers (M1, M2) of Ansari et al. (2018) are compared with proposed multipliers. The proposed 8-bit multipliers of either Type-1 or Type-2 work with the maximum delay of 245ps, whereas the existing designs work with maximum delay of 300ps. The proposed designs have constant delay and also nearly 40% energy savings for increase in ER of 2% and the MED increment of 0.72, 3 when compared to M1 and M2 designs respectively. The proposed multiplier effectiveness is demonstrated using image smoothing, edge detection, and Discrete Cosine Transform (DCT), resulting in high acceptable values for quality metrics of Average PSNR, SSIM, and PIQE. The PSNR for DCT is 28 dB with SSIM of 0.99 and PIQE of 42.9.

Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application

Abstract: In this work, low-voltage high-performance, fully differential current mirror Operational Transconductance Amplifiers (OTAs) are designed using DTMOS and asymmetric threshold voltage self cascode structure. Additionally cross drain coupled positive feedback and auxiliary slew-rate enhancement (SRE) technique are employed to improve the gain and slew-rate of proposed circuits. The proposed-I OTA (OTA-1) utilizes the dynamic threshold metal oxide semiconductor (DTMOS) technique which operates at low supply voltage and provides enhanced performance. However, the asymmetric threshold voltage self cascode structure used in proposed-II OTA (OTA-2) further improves the gain and other parameters. The proposed OTAs operate at ± 0.4 V dual power supply. The open-loop gain for the OTA-1 and OTA-2 is obtained as 73 dB and 82 dB with 10.04 μW and 10.77 μW power consumption, respectively. It offers enhanced slew-rate and improved GBW than the conventional OTA. Moreover, it gives high CMRR as 216 dB and 250 dB for the OTA-1 and OTA-2 respectively. The universal biquad voltage-mode filter has been realized using proposed OTAs. All simulations are performed using Mentor Graphics Eldo simulation tool with TSMC 0.18 μm process parameters. To validate the robustness of proposed OTAs, Monte Carlo analysis and corner analysis have been performed.

Integrated DC - DC converter design methodology for design cycle speed up

Abstract: A novel design methodology, enabling extreme design cycle time speed up of DC - DC power converters, is developed. The concept is based on providing high accuracy post-layout RC parasitics aware results, by replacing complicated large RC netlists with small signal approximation models. Scattering parameters analysis is adopted for “on the fly” performance simulation of the power MOSFET switches' routings, which act as large passive linear networks. The RC parasitics aware back end of line (BEOL) S-parameter model is extracted and seamlessly integrated into the schematic testbench, considering the actual circuit as a black box and therefore actively cutting down the design's netlist size to minimum values. Thus, the DC – DC converter performance degradation, that previously could not be simulated, now is accurately predicted and evaluated while the respective simulation time and the number of design iterations needed from layout (physical design) to the schematic and vice versa, are minimized. The proposed methodology is validated using an Integrated Pulse Width Modulation controlled DC - DC converter product vehicle, for light energy harvesting applications, designed, simulated and fabricated in a 0.18 μm CMOS standard process. Experimental results confirm the accuracy and design cycle speed up effectiveness of the proposed novel IC power converter design methodology.

An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications

Abstract: The mortality rate due to cardiac abnormalities is enormous, making the development of wearables to monitor functioning of the heart of paramount importance. In this paper, wepresent a resource efficient and low power architecture using Integer Haar Wavelet Transform for the complete delineation of ECG signal. The novelty of the algorithm lies in the use of single scale wavelet coefficients to delineate P-QRS-T features making it computationally simple. The proposed architecture is implemented using Xilinx FPGA ZedBoard Zynq™ −7000 platform, and utilises only 4.38% of the available resources. It is synthesised using 180 nm CMOS technology consuming 0.88 μW power, making it area as well as power-efficient for the wearable IoT healthcare devices.

Convex optimization of random dynamic voltage and frequency scaling against power attacks

Abstract: Convex optimization is explored in this paper to maximize the security against power analysis attacks while minimizing the power and performance overheads for a cryptographic circuit employs a random dynamic voltage and frequency scaling (RDVFS) technique. To realize this optimization goal, firstly, non-convex functions are used for modeling all the critical parameters related to the RDVFS technique to create a non-convex objective function. Subsequently, the non-convex objective function is appropriately converted into a convex objective function in order to grab the global optimum value. By transforming the acquired convex objective function into the Lagrange dual function and using Karush–Kuhn–Tucker (KKT) conditions to solve this optimization problem, the best RDVFS strategy can be uncovered. As shown in the result, after employing convex optimization for a cryptographic circuit with a RDVFS technique, the corresponding figure-of-merit (FOM) is enhanced by 43.4%. Moreover, in comparison with the conventional machine learning technique, the proposed convex optimization technique improves the overall FOM related with RDVFS technique by 17.6% while reducing 85.3% computational time.

Constructing keyed strong S-Box with higher nonlinearity based on 2D hyper chaotic map and algebraic operation

Abstract: As the only nonlinear component, S-Box plays an important role in cryptography. To overcome the problems in some 1D chaotic maps such as poor randomness and lacking ergodicity, we constructed a 2D exponential quadratic chaotic map (2D-EQCM), and analyzed its dynamic behavior through phase diagram, Lyapunov exponent, Kolmogorov entropy, correlation dimension and randomness testing. The results demonstrated that the 2D-EQCM with ergodicity and better randomness can be served as pseudo-random number generator (PRNG). Furthermore, to generate a large number of S-Boxes with higher nonlinearity, we designed a keyed strong S-Box construction algorithm using the 2D-EQCM and algebraic operation based on seed S-Boxes. Experimental results verified the effectiveness of the proposed keyed strong S-Box construction algorithm.

Mathematical analysis and circuit emulator design of the three-valued memristor

Abstract: Compared with the two-valued memristor, the three-valued memristor has higher data density, richer dynamic characteristics, and more potential in digital logic and chaotic circuit. The present model of the three-valued memristor has several limitations. It doesn't perform well enough in three-valued applications since its hysteresis loops are linear and asymmetric. The mathematical model of the three-valued memristor with nonlinear and symmetric hysteresis loops is proposed in this research. To further investigate the electrical characteristics of the three-valued memristor, a circuit emulator of the memristor has been constructed with fundamental components. Multisim simulations and hardware experiments demonstrate the emulator's effectiveness. The three-valued memristor application in chaotic circuits shows fascinating dynamic characteristics and lays the foundation for future research.

A transparent virtual channel power gating method for on-chip network routers

Abstract: Since static power gradually dominates on-chip network power, power gating has been widely studied as a way to mitigate this trend. Even though many power gating methods reduce static power, they introduce new problems such as higher latency and hardware overhead, network disconnections, and low scalability. A new power gating method is therefore needed that can effectively reduce static power without sacrificing the benefits of the on-chip network. In this paper, we propose an efficient power gating method for virtual channels. Firstly, neighboring routers no longer exchange and store each other’s power states with handshake signals, and each router independently decides when to sleep or wake up based on traffic loads. Secondly, in order to eliminate flit stalls and reduce network latency, we propose a modified credit-based flow control and provide a detailed hardware implementation. Finally, bypasses allow packets to reach processing elements (PEs) or downstream routers without waking up sleeping virtual channels, which reduces breakeven time (BET) violations and cumulative wake-up latency while ensuring network connectivity. Based on the evaluation, under real applications, the proposed power gating method reduces static energy by an average of 82.5% compared to the baseline, while increasing latency overhead by 13.7% and area overhead by 6.48%.

Edge computing design space exploration for heart rate monitoring

Abstract: Edge computing, smart sensors, and health monitoring are boosting current wearable development and enabling the next technological user-centred revolution. Within this context, high added-value applications based on physiological information are gaining attention during the last years. Among the vast physiological metrics available, heart rate variability (HRV) is one of the most used. From such metric, different types of information related to the activity of the autonomic nervous system can be obtained. This fact has led integrated chip manufacturers to foster the design of novel analog front end circuitry for heart rate monitoring, which boosted a wearable smart sensor innovation. Notwithstanding the capabilities and efficiency of these novel sensors, different design space exploration (DSE) procedures must be addressed for every sensor integrated within any wearable system towards maximising the embedded resource usage. On this basis, this paper presents a DSE breakup for every stage involved in a wearable edge device developed by the authors and based on continuous HRV physiological monitoring. The particularities of such a system are detailed and explained. Moreover, time complexity and memory usage comparisons regarding different digital signal processing techniques are provided, which results in a set of potential recommendations for wearable constrained application needs. Finally, a use case is presented based on a rapid stress detection application by using the different DSE recommendations for our specific wearable edge device. This application reaches adequate trade-off precision for detecting physiological HRV activation using only a four-second temporal processing window. • Design Space Exploration is an essential task when facing the development of physiological edge computing devices. • The different morphology of PPG signals directly affects the data processing chain of HR-based wearable devices. • Heart Rate Variability is a reliable metric to detect physiological activation.

Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC

Abstract: The Two-Dimensional Fast Fourier Transform (2D-FFT) algorithm is used for the study of many modern systems applied for security and biometrics. The adoption of this algorithm, which is a compute intensive task, is limited due to its hardware design complexity. The first objective of this paper is to underline the effect of the hardware/software co-design (Hw/Sw co-design) for the reduction of the processing time and power consumption. Secondly, we propose an innovative architecture for the 2D-FFT algorithm tested on Zynq Soc, which requires less processing time and memory compared to the traditional algorithm. Three implementations (one software and two Hw/Sw co-designs) of the 2D-FFT algorithm using the Zynq SoC are presented in this paper. The first is based on ARM processor. A speedup of 29x is obtained compared to the original implementation thanks to many optimizations. The second is a Hw/Sw co-design solution of the traditional 2D-FFT algorithm introduced on a hybrid platform combining an ARM Cortex-A9 processor with an FPGA. The third is also a Hw/Sw co-design solution using our optimized 2D-FFT algorithm to reach the real-time contraints for high-resolution images (1920 × 1080). It provides a speedup of 1.13x, 3.31x and 96.21x faster than the Hw/Sw co-design implementation of the traditional RC algorithm, the pure software implementations with and without optimizations, respectively.

Neural network <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" display="inline" id="d1e1073" altimg="si208.svg"><mml:msub><mml:mrow><mml:mi>ℒ</mml:mi></mml:mrow><mml:mrow><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:math> adaptive control for a class of uncertain fractional order nonlinear systems

Abstract: This research work presents an ℒ1 adaptive control scheme based on a fractional-order sliding surface and a Radial Basis Function (RBF) neural network, for a general class of uncertain fractional-order nonlinear systems. The structure of the proposed controller is composed of a predictor, a control law, an adaptive mechanism and an RBF neural network. The latter is designed as an estimator in the controller architecture to handle and approximate nonlinear uncertain dynamics. The estimation loop in the proposed Neural Network (NN) fractional-order ℒ1 adaptive controller is decoupled from the control loop thanks to the use of a filter in the input channel, which makes it possible to preserve the robustness while enhancing transient performances. Besides, the suggested controller guarantees the closed-loop system’s stability with bounded transient and tracking performances. Finally, the effectiveness and efficiency of the proposed controller are put on test using numerical simulations and comparative studies.

Valid test pattern identification for VLSI adaptive test

Abstract: With continuously decreasing circuit scale, more and more test patterns (test contents) are added to test set to achieve acceptable defect levels, which seriously affect test time and, consequently, test cost. Theoretically, dropping invalid (pattern that can make the test pass) test patterns can reduce test cost. In fact, When the valid (pattern that can make the test fail) and invalid patterns overlap seriously, identifying effective patterns performs poorly, which will not achieve the expected results. This paper proposes a kind of eliminate redundancy method, so that this LDA-MRMR algorithm which can provide test cost reduction without increasing the defect level obviously. Experimental results demonstrate that the proposed method sacrifices 3% of the predictive accuracy in exchange for 3.7 times time saving compared with traditional methods. In addition, the algorithm is completely software-based and does not require any additional hardware overhead and is directly compatible with traditional integrated circuit testing process.