Showing papers in "Integration in 2022"

TL;DR: In this paper , a dual-mode configurable and tunable power amplifier (PA) that achieves a widebandwidth and high gain across a operational frequency spectrum of 20 to 30 GHz is presented.

TL;DR: In this paper , a hybrid method called Scored Regional Congestion Aware and DICA (ScRD) is proposed to select a better output channel and increase NOC performance.

TL;DR: In this article , a high-level security is achieved by chaotic sequences generated by a robust chaos-based PRNG based on the Lorenz, Chua, Rossler, and Chen chaotic maps.

TL;DR: Agile-AES as discussed by the authors is an open-source, flexible, parameterizable, hardware implementation of AES, combining many best-known practices, through which flexibility is instrumented to support various key length, topology, mode of operation, local memory type, S-box fabric, and interfaces.

TL;DR: In this paper , an application pattern driven dynamic routing approach for NoC based systems while committed to optimize desired performance parameters is proposed, which serves a dual purpose of improving the network performance of the NoC-based system as well as relieving the design engineers from making the complex and tedious routing decisions.

TL;DR: A comprehensive review of recent advances in the design automation of CFMBs, including CAD techniques for architecture synthesis, volume assignment and sample preparation, testing, fault-tolerant design, and washing, is presented in this paper .

TL;DR: In this article , the authors proposed to integrate information from the output responses corresponding to different input stimuli and to use the combined information to improve the accuracy of fault diagnosis in analog circuits.

TL;DR: In this paper , the authors proposed a watermarking scheme for image authentication and recovery of tampered images based on block truncation coding (BTC) and singular value decomposition (SVD).

TL;DR: In this article , a novel symmetrical four-wing fourth-order chaotic system is constructed and the basic dynamic characteristics of the system were analyzed by phase diagram, bifurcation diagram, Lyapunov index spectrum, Poincare cross section diagram and 0-1 test.

TL;DR: In this article , a novel four-dimensional autonomous chaotic system based on memristive diode bridge is presented, and it consists of a simple linear oscillation and a memristor.

TL;DR: In this article , a simple chaotic oscillator is designed by using three grounded capacitors, six transistors and an external comparator sub-circuit as a signum nonlinearity function in a feedback loop.

TL;DR: Wang et al. as discussed by the authors proposed a Wafer map defect pattern (WDP-BNN) framework based on the binarized neural network to reduce memory requirement by 29.70× and speed up by 1.66×.

TL;DR: Wang et al. as discussed by the authors constructed a four-dimensional multi-scroll hyperchaotic system, which is suitable for image encryption due to their numerous intrinsic properties such as stability of equilibrium point, dissipation attractors, Lyapunov exponent spectrum, and bifurcation diagram.

TL;DR: In this paper , the authors proposed an improved KNN algorithm to classify the defects, i.e., this TP selection approach utilizes a classification model to select the valid patterns only, to shorten the Test Time (TT).

TL;DR: In this article , a survey of recent research works on M3D technology from the computer system perspective with several case studies, and presents the opportunities as well as the challenges brought by this emerging technology.

TL;DR: In this article , a new low-power fulladder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology.

TL;DR: In this article , the authors proposed a novel ultra-lightweight block cipher DULBC based on a dynamic SPN structure, which adopts an unfixed F-function and a bit-based permutation.

TL;DR: In this paper , a new chaotic memristor system based on a well-known nonlinear circuit is proposed, which can reduce the number of active elements and reduce power consumption.

TL;DR: In this paper , the authors proposed a constant carry-based approximate compressors for partial product reduction in the binary multiplier, which have only Sum as output and the output carry bits are either constant 0 or 1 and hence no requirement of logic computation.

TL;DR: In this article , a low-voltage high-performance, fully differential current mirror Operational Transconductance Amplifiers (OTAs) are designed using DTMOS and asymmetric threshold voltage self cascode structure.

TL;DR: In this article , a novel design methodology is developed to enable extreme design cycle time speed up of DC-DC power converters, based on providing high accuracy post-layout RC parasitics aware results, by replacing complicated large RC netlists with small signal approximation models.

TL;DR: In this article , a resource efficient and low power architecture using Integer Haar Wavelet Transform (IHT) for the complete delineation of ECG signal has been presented, which uses single scale wavelet coefficients to delineate P-QRS-T features making it computationally simple.

TL;DR: In this article , a non-convex objective function is used for modeling all the critical parameters related to the random dynamic voltage and frequency scaling (RDVFS) technique.

TL;DR: Wang et al. as discussed by the authors constructed a 2D exponential quadratic chaotic map (2D-EQCM), and analyzed its dynamic behavior through phase diagram, Lyapunov exponent, Kolmogorov entropy, correlation dimension and randomness testing.

TL;DR: In this article , the authors proposed a mathematical model of the three-valued memristor with nonlinear and symmetric hysteresis loops and constructed a circuit emulator with fundamental components.

TL;DR: In this paper , the authors proposed a power gating method for virtual channels, where neighboring routers no longer exchange and store each other's power states with handshake signals, and each router independently decides when to sleep or wake up based on traffic loads.

TL;DR: In this article , the authors present a DSE breakup for every stage involved in a wearable edge device developed by the authors and based on continuous heart rate variability (HRV) physiological monitoring.

TL;DR: In this paper , the authors proposed an innovative architecture for the 2D-FFT algorithm tested on Zynq Soc, which requires less processing time and memory compared to the traditional algorithm.

TL;DR: In this article , a fractional-order sliding surface and a Radial Basis Function (RBF) neural network are used to handle nonlinear uncertain dynamics in a closed-loop system.

TL;DR: In this article , the authors proposed a kind of eliminate redundancy method, so that this LDA-MRMR algorithm which can provide test cost reduction without increasing the defect level, which can sacrifice 3% of the predictive accuracy in exchange for 3.7 times time saving compared with traditional methods.