International Journal of Parallel, Emergent and Distributed Systems 

About: International Journal of Parallel, Emergent and Distributed Systems is an academic journal published by Taylor & Francis. The journal publishes majorly in the area(s): Computer science & Wireless sensor network. It has an ISSN identifier of 1744-5760. Over the lifetime, 620 publications have been published receiving 5673 citations. The journal is also known as: IJPEDS & Parallel, emergent and distributed systems.

Time-varying graphs and dynamic networks

Abstract: The past few years have seen intensive research efforts carried out in some apparently unrelated areas of dynamic systems – delay-tolerant networks, opportunistic-mobility networks and social networks – obtaining closely related insights. Indeed, the concepts discovered in these investigations can be viewed as parts of the same conceptual universe, and the formal models proposed so far to express some specific concepts are the components of a larger formal description of this universe. The main contribution of this paper is to integrate the vast collection of concepts, formalisms and results found in the literature into a unified framework, which we call time-varying graphs TVGs. Using this framework, it is possible to express directly in the same formalism not only the concepts common to all those different areas, but also those specific to each. Based on this definitional work, employing both existing results and original observations, we present a hierarchical classification of TVGs; each class corresponds to a significant property examined in the distributed computing literature. We then examine how TVGs can be used to study the evolution of network properties, and propose different techniques, depending on whether the indicators for these properties are atemporal as in the majority of existing studies or temporal. Finally, we briefly discuss the introduction of randomness in TVGs.

Performance and accuracy of hardware-oriented native-, emulated-and mixed-precision solvers in FEM simulations

Abstract: In this survey paper, we compare native double precision solvers with emulated-and mixed-precision solvers of linear systems of equations as they typically arise in finite element discretisations. The emulation utilises two single float numbers to achieve higher precision, while the mixed precision iterative refinement computes residuals and updates the solution vector in double precision but solves the residual systems in single precision. Both techniques have been known since the 1960s, but little attention has been devoted to their performance aspects. Motivated by changing paradigms in processor technology and the emergence of highly-parallel devices with outstanding single float performance, we adapt the emulation and mixed precision techniques to coupled hardware configurations, where the parallel devices serve as scientific co-processors. The performance advantages are examined with respect to speedups over a native double precision implementation (time aspect) and reduced area requirements for a chip (space aspect). The paper begins with an overview of the theoretical background, algorithmic approaches and suitable hardware architectures. We then employ several conjugate gradient (CG) and multigrid solvers and study their behaviour for different parameter settings of the iterative refinement technique. Concrete speedup factors are evaluated on the coupled hardware configuration of a general-purpose CPU and a graphics processor. The dual performance aspect of potential area savings is assessed on a field programmable gate array (FPGA). In the last part, we test the applicability of the proposed mixed precision schemes with ill-conditioned matrices. We conclude that the mixed precision approach works very well with the parallel co-processors gaining speedup factors of four to five, and area savings of three to four, while maintaining the same accuracy as a reference solver executing everything in double precision.

Concurrent number cruncher: a GPU implementation of a general sparse linear solver

Abstract: A wide class of numerical methods needs to solve a linear system, where the matrix pattern of non-zero coefficients can be arbitrary. These problems can greatly benefit from highly multithreaded computational power and large memory bandwidth available on graphics processor units (GPUs), especially since dedicated general purpose APIs such as close-to-metal (CTM) (AMD-ATI) and compute unified device architecture (CUDA) (NVIDIA) have appeared. CUDA even provides a BLAS implementation, but only for dense matrices (CuBLAS). Other existing linear solvers for the GPU are also limited by their internal matrix representation. This paper describes how to combine recent GPU programming techniques and new GPU dedicated APIs with high performance computing strategies (namely block compressed row storage (BCRS), register blocking and vectorization), to implement a sparse general-purpose linear solver. Our implementation of the Jacobi-preconditioned conjugate gradient algorithm outperforms by up to a factor of 6.0 × leading-edge CPU counterparts, making it attractive for applications which are content with single precision.

Journeys in non-classical computation I: A grand challenge for computing research

Abstract: 1. The challengeA gateway event [35] is a change to a system that leads to the possibility of huge increases inkinds and levels of complexity. It opens up a whole new kind of phase space to the system’sdynamics.Gatewayeventsduringevolutionoflifeonearthincludetheappearanceofeukaryotes(organisms with a cell nucleus), an oxygen atmosphere, multi-cellular organisms and grass.Gatewayeventsduringthedevelopmentofmathematicsincludeeachinventionofanewclassofnumbers (negative, irrational, imaginary, ...), and dropping Euclid’s parallel postulate.A gateway event produces a profound and fundamental change to the system: Oncethrough the gateway, life is never the same again. We are currently poised on the threshold ofa significant gateway event in computation: That of breaking free from many of our current“classical computational” assumptions. Our Grand Challenge for computer science isto journey through the gateway event obtained by breaking our current classicalcomputational assumptions, and thereby develop a mature science of Non-ClassicalComputation2. Journeys versus goals

Electric vehicle smart charging and vehicle-to-grid operation

Abstract: Electric vehicle EV charging must be optimised for grid load while guaranteeing that drivers' schedules and range requirements are met. A system encompassing EV owner input via a mobile application, an aggregation middleware, a charge scheduling and vehicle-to-grid V2G operation algorithm and a radio-frequency identification reader is proposed. The algorithm's parameters and effectiveness are presented and discussed using simulation results. Simulation results show the algorithm to effectively optimise charging and V2G operation for a given electricity price curve. The proposed system is shown to alleviate grid load during peak hours, take advantage of off-peak charging benefits and generate revenue for the parking garage operator.