Proceedings ArticleDOI
400 Gb/s Programmable Packet Parsing on a Single FPGA
Michael E. Attig,Gordon J. Brebner +1 more
- pp 12-23
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TLDR
PP: a simple high-level language for describing packet parsing algorithms in an implementation-independent manner is introduced and it is demonstrated that this language can be compiled to give high-speed FPGA-based packet parsers that can be integrated alongside other packet processing components to build network nodes.Abstract:
Packet parsing is necessary at all points in the modern networking infrastructure, to support packet classification and security functions, as well as for protocol implementation. Increasingly high line rates call for advanced hardware packet processing solutions, while increasing rates of change call for high-level programmability of these solutions. This paper presents an approach for harnessing modern Field Programmable Gate Array (FPGA) devices, which are a natural technology for implementing the necessary high-speed programmable packet processing. The paper introduces PP: a simple high-level language for describing packet parsing algorithms in an implementation-independent manner. It demonstrates that this language can be compiled to give high-speed FPGA-based packet parsers that can be integrated alongside other packet processing components to build network nodes. Compilation involves generating virtual processing architectures tailored to specific packet parsing requirements. Scalability of these architectures allows parsing at line rates from 1 to 400 Gb/s as required in different network contexts. Run-time programmability of these architectures allows dynamic updating of parsing algorithms during operation in the field. Implementation results show that programmable packet parsing of 600 million small packets per second can be supported on a single Xilinx Virtex-7 FPGA device handling a 400 Gb/s line rate.read more
Citations
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Ibex: an intelligent storage engine with support for advanced SQL offloading
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Design principles for packet parsers
TL;DR: Trade-offs in parser design are described, design principles for switch and router designers are identified, and a parser generator that outputs synthesizable Verilog is described that is available for download.
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Scalable ternary content addressable memory implementation using FPGAs
TL;DR: This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs, and is the first FPGA design that implements a TCAM larger than 1 Mbits.
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StrideBV: Single chip 400G+ packet classification
TL;DR: This work presents a bit vector based lookup scheme and a parallel hardware architecture that does not rely on ruleset features and post place-and-route results of the parallel pipelined architecture on a state-of-the-art Field Programmable Gate Array (FPGA) device shows that for real-life firewall rulesets, the proposed solution achieves 400G+.
Journal ArticleDOI
High-Speed Packet Processing using Reconfigurable Computing
Gordon J. Brebner,Weirong Jiang +1 more
TL;DR: A tool chain is presented that maps a domain-specific packet-processing language called PX to high-performance reconfigurable-computing architectures based on field-programmable gate array (FPGA) technology.
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