Proceedings ArticleDOI
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems
Hiroe Iwasaki,Jiro Naganuma,Yasuyuki Nakajima,Yutaka Tashiro,Ken Nakamura,Takeshi Yoshitome,Takayuki Onishi,Mitsuo Ikeda,T. Izuoka,Endo Makoto +9 more
- pp 177-180
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This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness.Abstract:Â
This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm/spl times/9.7 mm die using the 0.13 /spl mu/m seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.read more
Citations
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Journal ArticleDOI
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level
Hiroe Iwasaki,Jirou Naganuma,Koyo Nitta,Ken Nakamura,Takeshi Yoshitome,Mitsuo Ogura,Yasuyuki Nakajima,Yutaka Tashiro,Takayuki Onishi,Mitsuo Ikeda,Toshihiro Minami,Endo Makoto,Yoshiyuki Yashima +12 more
TL;DR: This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness.
Journal ArticleDOI
New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex codec LSI
TL;DR: This set-top box with home television set provides standard-TV-quality bi-directional video transmission via commercially available FTTH-based IP broadband network.
Journal ArticleDOI
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline
TL;DR: An elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits and achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.
References
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Journal ArticleDOI
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking
Masayuki Mizuno,Y. Ooi,N. Hayashi,J. Goto,M. Hozumi,Koichiro Furuta,Atsufumi Shibayama,Y. Nakazawa,O. Ohnishi,Shu-Yu Zhu,Y. Yokoyama,Y. Katayama,H. Takano,N. Miki,Yuzo Senda,I. Tamitani,Masakazu Yamashina +16 more
TL;DR: A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed and developed low-power clocking techniques, which can eliminate waste of power in clocking.
Journal ArticleDOI
A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H/spl plusmn/288, V:/spl plusmn/96) motion estimation and 81-MOPS controller
TL;DR: An MPEG2 MP@ML video encoder large-scale integrated circuit (LSI) has been developed including an 81 MOPS controller and motion estimator including a wide motion-estimation search area and there is a significant improvement in picture quality for coding fast motion sequences.
Proceedings ArticleDOI
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level
Hiroe Iwasaki,Jiro Naganuma,Koyo Nitta,Ken Nakamura,Takeshi Yoshitome,Mitsuo Ogura,Yasuyuki Nakajima,Yutaka Tashiro,Takayuki Onishi,Mitsuo Ikeda,Endo Makoto +10 more
TL;DR: A new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, is proposed and demonstrates its flexibility and usefulness.
Proceedings ArticleDOI
A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller
E. Miyagoshi,T. Araki,T. Sayama,A. Ohtani,T. Minemaru,K. Okamoto,H. Kodama,T. Morishige,A. Watabe,K. Aoki,T. Mitsumori,H. Imanishi,T. Jinbo,Y. Tanaka,M. Taniyama,T. Shingou,T. Fukumoto,H. Morimoto,Kunitoshi Aono +18 more
TL;DR: An MPEG2 MP@ML video encoder system can be realized with two 16 Mb SDRAMs controlled by the MIF in the VDSP3, which is a single-chip MPEG2 video encoding system similar to that of a previous LSI.
A 99-mm^2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system
TL;DR: The encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture, which results in a PC-card size 422p@HL encoderWith lowest power consumption for portable HDTV codec system.
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