Patent
A complementary low power non-volatile reconfigurable eecell
John E. Turner,Richard G. Cliff +1 more
Reads0
Chats0
TLDR
In this article, a nonvolatile CMOS electrically erasable programmable memory cell for configuring a PLD is described, which is formed by fabricating an n-channel MOSFET and a p-channel MCFET with merged floating gate regions.Abstract:
A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floating gate. The floating gate provides non-volatile charge storage. The CMOS inverter senses the presence or absence of charge on the floating gate and provides an amplified inverted output. The CMOS inverter consumes very low power and provides rail-to-rail output voltage swings.read more
Citations
More filters
Patent
Non-volatile memory device and method of fabricating the same
TL;DR: In this article, a non-volatile memory device may include at least one semiconductor column, and a charge storage layer may be between the first gate and the second gate.
Patent
Nonvolatile configuration cells and cell arrays
TL;DR: In this article, a memory cell (400) is used to store data in an integrated circuit and a pull-down device (525) is coupled between another supply voltage (505) and the output node (405).
Patent
Nonvolatile SRAM cells and cell arrays
TL;DR: In this paper, the memory cell (400) is used to store the configuration information of a programmable logic device (121) for storing data on an integrated circuit (IC).
Patent
Floating gate inverter type memory cell and array
Mikalai Audzeyeu,Yuriy Makarevich,Siarhei Shvedau,Anatoly Belous,Evgeny Pikhay,Vladislav Dayan,Yakov Roizin +6 more
TL;DR: In this article, a nonvolatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit, which is programmed/erased by Fowler-Nordheim tunneling.
Patent
CMOS EEPROM cell with tunneling window in the read path
TL;DR: In this paper, a CMOS memory cell including PMOS and NMOS transistors with a common floating gate is presented, which includes a first capacitor connecting a first control voltage to the common floating-gate and a second tunneling capacitor connected from the common fixed gate to the source of the NMOS transistor.
References
More filters
Patent
Improved logic cell array using CMOS E2 PROM cells
TL;DR: In this paper, a programmable memory cell with a common floating gate is presented, where the floating gate comprises a first polycrystalline silicon layer (polysilicon), and a second polysilicon layer spaced from and capacitively coupled with the first poly-silicon layers is utilized to selectively applying charge to the common floating-gate.
Patent
Zero power, electrically alterable, nonvolatile latch
Vikram Kowshik,Elroy M. Lucero +1 more
TL;DR: In this article, a compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with a single layer of polysilicon.
Patent
Optimized electrically erasable cell for minimum read disturb and associated method of sensing
Nader Radjy,Michael S. Briner +1 more
TL;DR: In this article, a non-volatile memory apparatus with a plurality of memory cells, each memory cell including a floating gate tunnel device (130) having a drain (134) and a floating-gate read transistor (140), having a source (142) and drain (144), with a common control gate (136, 146).
Patent
E2 prom cell including isolated control diffusion
TL;DR: In this paper, an improved EEPROM has a cell including source and drain diffusions, a channel having a source region and a drain region, a floating gate that is disposed only over the drain region of the channel and has a coupling edge disposed adjacent to the drain diffusion to strongly capacitively couple the floating gate to the sink.
Patent
Non-volatile memory device
TL;DR: In this paper, a non-volatile memory device includes a memory cell array composed of transistor memory cells, a monitor cell array consisting of two transistor monitor cells, and a first circuit for writing "0" and then "1" in the first monitor cell and a data "1, then "0", in the second monitor cell, whenever a data is written in one of the memory cells.