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Proceedings ArticleDOI

A high-performance host interface for ATM networks

C. Brendan S. Traw, +1 more
- Vol. 21, Iss: 4, pp 317-325
TLDR
A host interface 1 for an asynchronous transfer mode (ATM) network comprises a Segmenter 2 and Reassembler 3, capable of reassembling an ATM cell in less than 2.7 microseconds.
Abstract
A host interface 1 for an asynchronous transfer mode (ATM) network comprises a Segmenter 2 and Reassembler 3. The host interface 1 is connected to a Sunshine ATM switch 7 via an electrical to optical converter 6 and an IBM RS/6000 workstation 4 via a MicroChannel bus 5. The Reassembler 3 comprises three components, respectively referred to as the Linked List Manager, Dual Port Reassembly Buffer and SONET Interface and VCI Lookup Controller, that are capable of concurrent operation once they are initialized and configured. Those components are capable of reassembling an ATM cell in less than 2.7 microseconds.

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References
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Journal ArticleDOI

Paris: An approach to integrated high‐speed private networks

TL;DR: This paper describes a design of a high-speed packet switching system for integrated voice, video and data communications that makes use of a simplified network architecture in order to achieve the low packet delay and high nodal throughput necessary for the transport of voice and video.
Journal ArticleDOI

The VMP network adapter board (NAB): high-performance network communication for multiprocessors

TL;DR: In this article, the authors propose a host-to-network adapter interface for high performance computer communication between multiprocessor nodes, which requires significant improvements over conventional HN adapters.
Patent

Signalling apparatus for use in an atm switching system

TL;DR: In this article, a subscriber line signalling apparatus for use in an asynchronous mode communication system includes a switching circuit having a plurality of input terminals and a pluralityof output terminals, and an adaptation processing unit reassembles the fixed length packets to signalling frames and transmits them to a frame processor.
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The VMP network adapter board (NAB): high-performance network communication for multiprocessors

TL;DR: The design of a network adapter board for the VMP multiprocessor machine is described, which uses a host interface that is designed for minimal latency, minimal interrupt processing overhead and minimal system bus and memory access overhead.
Journal ArticleDOI

The design of nectar: a network backplane for heterogeneous multicomputers

TL;DR: The motivation and goals for Nectar are presented and its hardware and software are described and the presentation emphasizes how the goals influenced the design decisions and led to the novel aspects of Nectar.
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Which ipv4 address can a host use to ping the loopback interface?

The host interface described in this paper is highly parallel and a pure hardware solution to maximize performance.