Patent
Active cache for a microprocessor
TLDR
In this paper, an active cache memory for use with microprocessors is disclosed, which is capable of performing transfers from external random access memory independently of the encache misaligned references and to transfer data to the microprocessor in bursts.Abstract:
An active cache memory for use with microprocessors is disclosed. The cache is external to the microprocessor and forms a second level cache which is novel in that it is capable of performing transfers from external random access memory independently of the encache misaligned references and to transfer data to the microprocessor in bursts.read more
Citations
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Patent
Semiconductor memory device and method of operating the same
TL;DR: In this paper, the authors propose a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, and a control logic for generating an address for the second main blocks in response to a dedicated command for access to one of the main blocks.
Patent
Non-volatile memory cache performance improvement
Cenk Ergan,Clark D. Nicholson,Dan Teodosiu,Dean L. DeWhitt,Emily Nicole Hill,Hanumantha Rao Kodavalla,Michael James Zwilling,John M. Parchem,Michael R. Fortin,Nathan Steven Obr,Rajeev Y. Nagar,Surenda Verma,Therron Powell,William J. Westerinen,Mark J. Zbikowski,Patrick L. Stemen +15 more
TL;DR: In this article, the non-volatile memory is used as a write buffer and a read cache for writes and reads to the long-term storage media and a direct mapping for specified sectors of the LSTM is provided.
Patent
Method for scheduling threads in a multithreaded processor
TL;DR: In this article, a method for scheduling execution of a plurality of threads executed in a multithreaded processor is presented. But the method is limited to a single thread and it is not suitable for multi-threaded systems.
Patent
Method for scheduling contexts based on statistics of memory system interactions in a computer system
Jeffrey Dean,Carl A. Waldspurger +1 more
TL;DR: In this paper, a method for scheduling execution contexts in a computer system based on memory interactions is proposed, where a processor and a hierarchical memory are arranged in a plurality of levels.
Patent
Storing a frame header
Uri Elzur,Dan G. Wartski +1 more
TL;DR: In this paper, a header indicates at least one characteristic that is associated with a layer of a protocol stack, and the header is parsed in hardware to extract the characteristic(s), and the packet is processed based on the parsing.
References
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Patent
Communication apparatus and methods
TL;DR: In this article, a multi-port packet-based bridge is described in which packet transmissions on particular ports or between ports may be monitored on another, monitoring port by using a Supervisory Access Terminal.
Patent
Method and apparatus for data transfer between source and destination modules
TL;DR: In this article, a multi-master global synchronous bus is optimized to perform fast block transfers between modules that communicate over a multiuser global synchronized bus, with a destination module sending a "ready-to-accept-data" signal before each write request.