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An efficient algorithm for exploiting multiple arithmetic units
R. M. Tomasulo
- pp 13-21
TLDR
In this article, the authors describe the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units and register tagging schemes.Abstract:
This paper describes the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units Basic to these techniques is a simple common data busing and register tagging scheme which permits simultaneous execution of independent instructions while preserving the essential precedences inherent in the instruction stream The common data bus improves performance by efficiently utilizing the execution units without requiring specially optimized code Instead, the hardware, by 'looking ahead' about eight instructions, automatically optimizes the program execution on a local basis The application of these techniques is not limited to floating-point arithmetic or System/360 architecture It may be used in almost any computer having multiple execution units and one or more 'accumulators' Both of the execution units, as well as the associated storage buffers, multiple accumulators and input/output buses, are extensively checkedread more
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References
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Journal ArticleDOI
The IBM System/360 model 91: machine philosophy and instruction-handling
TL;DR: It is shown that history recording (the retention of complete instruction loops in the CPU) reduces the need to exercise storage, and that sophisticated employment of buffering techniques has reducedt he effective access time.
Journal ArticleDOI
The IBM system/360 model 91: floating-point execution unit
TL;DR: The principal requirement for the Model 91 floating-point execution unit was that it be designed to support the instructionissuing rate of the processor, so separate, instruction-oriented algorithms for the add, multiply, and divide functions were developed.