Journal ArticleDOI
An efficient algorithm for single and multiple fault test sets generation
TLDR
In this article, a direct approach for single and multiple fault test set generation on any number of lines of a logical circuit has been described, for which only some visual inspections are needed rather than going through tedious steps of algebraic manipulations.Abstract:
A direct approach for single and multiple fault test set generation on any number of lines of a logical circuit has been described in this paper. The present paper simplifies the results of Ku and Masson [2] for which only some visual inspections are needed rather than going through tedious steps of algebraic manipulations. This method is thus easily applicable to arbitrarily large combinational circuits, whether it is fan-out free or with fan-out nodes.read more
Citations
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Journal ArticleDOI
A novel design of a combinational network to facilitate fault detection
TL;DR: In this article, the authors describe a combinational network to facilitate the single stuck-at fault detection problem, which makes use of EXCLUSIVE-OR modules as control elements and the observability has been increased by providing an observable output which is the output of an additional AND gate in the network.
Journal ArticleDOI
A graph-theoretic multiple logic fault analysis through Petri-nets
TL;DR: A new and a graph theoretic approach based on Petrinet model for calculating any order Boolean Difference has been suggested and is suitable for machine computation and is therefore, applicable to arbitrarily large circuits.
References
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Journal ArticleDOI
Analyzing Errors with the Boolean Difference
TL;DR: It is shown through example how the Boolean difference is used to analyze the effect of errors on the outputs of logic circuits.
Journal ArticleDOI
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
Stephen S. Yau,Yu-Shan Tang +1 more
TL;DR: An algorithm for generating the complete test set of each stuck-at-0 and stuck- at-1 single fault in a combinational logic circuit is presented and some ideas on the construction of test sets for detecting multiple faults based on Boolean differences are presented.
Journal ArticleDOI
The Boolean Difference and Multiple Fault Analysis
Chia-Tai Ku,G.M. Masson +1 more
TL;DR: This paper extends the Boolean difference concept to cover multiple fault situations and develops expressions which give all possible input patterns that can be applied to combinational logic circuits to demonstrate the presence or absence of a specified multiple fault of the stuck-type class.
Journal ArticleDOI
Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences
TL;DR: An algorithm for obtaining minimal, complete sets of test-input sequences based on the partial Boolean differences of a switching function is formulated, and illustrations demonstrating the use of the technique are presented.
Journal ArticleDOI
Boolean Difference Calculus and Fault Finding
TL;DR: In this paper, a method is devised for testing for a possible fault in a gate in a larger switching circuit, that does not require isolating the suspicious gate from the rest of the circuit.
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