Patent
Apparatus and method for program level parallelism in a VLIW processor
TLDR
A very long instruction word (VLIW) processor as discussed by the authors exploits program level parallelism as well as Instruction Level Parallelism (ILP) by providing new instruction level mechanisms to separate processor execution into parallel threads.Abstract:
A very long instruction word (VLIW) processor exploits program level parallelism as well as instruction level parallelism. Unlike prior VLIW machines which obtain speed advantages using instruction level parallelism, the present processor exploits the parallelism inherent in a VLIW processor by providing new instruction level mechanisms to separate processor execution into parallel threads. This separation allows greater hardware use because more than one program can exploit instruction level parallelism on the system at the same time. A first program and a second program execute concurrently such that the second program executes using resources and cycles that would have been wasted by the first program. This construct is especially useful where the second program is an interrupt service routine because the interrupt service routine can be threaded through the machine with high or low priority while the functional units still process the first program stream. A superscalar version of the processor is also described.read more
Citations
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References
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Journal ArticleDOI
Simultaneous multithreading: a platform for next-generation processors
TL;DR: Because simultaneous multithreading successfully (and simultaneously) exploits both types of parallelism, SMT processors use resources more efficiently, and both instruction throughput and speedups are greater.
Journal ArticleDOI
A VLIW architecture for a trace scheduling compiler
TL;DR: The TRACETM as mentioned in this paper is a very long instruction word (VLIW) compiler that computes ordinary sequential code into long instruction words, which is used in the Trace SchedulingTM compacting compiler.
Patent
Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
TL;DR: In a parallel data processing system, very long instruction words (VLIW) define operations able to be executed in parallel as mentioned in this paper, and the VLIWs corresponding to plural threads of computation are made available to the processing system simultaneously.
Patent
Multi-threaded microprocessor architecture utilizing static interleaving
Jin-Chin Chung,Chuan-Lin Wu +1 more
TL;DR: In this paper, a static interleaving technique is proposed to solve the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture, where each function unit in the processor is allocated for the execution of an instruction from a particular thread in a fixed predetermined time slot in a repeating pattern of predetermined time slots.
Patent
Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
TL;DR: In this article, a method of using multithreading resources for improving handling instructions is operated by an improved multithreaded processor which includes a context select logic unit being arranged and configured for receiving and responding an interrupt including a first controller for setting a pending thread latch when a hardware context is not available for executing a new thread for servicing the interrupt.