Patent
Apparatus and method for recursive parallel and pipelined fast fourier transform
TLDR
In this paper, a transposeless 2-dimensional FFT with minimum number of clock cycles and minimum complexity is presented. But the complexity of the circuit is reduced by elimination of butterfly computation structure and adaptation of transpose-less 2D transform architecture.Abstract:
A circuit for performing Fast Fourier Transform (FFT) with minimum number of clock cycles and minimum complexity. One-dimensional FFT of size N=N 0 ×N 1 × . . . ×N M−1 , N m m=0, 1, . . . , M−1, positive numbers, is computed recursively, through a sequence of two-dimensional row-column transform computations of sizes, N 0 ×N 1 , (N 0 ×N 1 )×N 2 , (N 0 ×N 1 ×N 2 )×N 3 , . . . , (N 0 ×N 1 × . . . ×N M−2 )×N M−1 with twiddle factors. The complexity of the circuit is reduced by elimination of butterfly computation structure and adaptation of transposeless 2-D transform architecture.read more
Citations
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Patent
Fast fourier transform twiddle multiplication
TL;DR: An FFT engine implementing a cycle count method of applying twiddle multiplications in multi-stages is described in this article, where the intermediate values need to be multiplied by various twiddle factors.
Patent
Pipelined low complexity FFT/IFFT processor
TL;DR: In this paper, a pipelined real-time N-point transform processor contains a first butterfly triplet multiplicatively connected to an output portion by way of a complex multiplier, and a reordering circuit is provided to insure that the order of the transformed complex numbers matches that of the input complex numbers.
Patent
Fast fourier transform processing in an OFDM system
TL;DR: In this article, a pipelined FFT engine using a shared memory architecture shared with channel estimation and demodulation blocks is proposed to enable the channel estimation to be completed during the time used to capture the next received symbol.
Patent
Fast fourier transform method and apparatus
Kevin R. Wadleigh,David Boyd +1 more
TL;DR: In this article, a method and apparatus for performing fast Fourier transform (FFT) for computers that can execute fused multiply-add instructions, especially suited for computers with the ability to execute FFT, is described.
Patent
High speed FFT hardware architecture for an OFDM processor
Debashis Goswami,Gagandeep Singh +1 more
TL;DR: In this article, a technique for providing high speed FFT architecture for OFDM processors that reduces silicon area while maintaining the high speed requirement is presented, which is accomplished by pipelined and/or sequential implementation of two or more FFT stages so that each stage performs a small portion of the FFT.
References
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Book
Discrete-Time Signal Processing
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
Journal ArticleDOI
A pipeline processor for mixed-size FFTs
TL;DR: A method for performing fast Fourier transforms of various sizes simultaneously in one pipeline processor that consists of several stages of butterfly computational elements alternated with delay-switch-delay modules that reorder the data between the butterfly stages.
Patent
Pipelined digital SAR azimuth correlator using hybrid FFT/transversal filter
Chialin Wu,Kuang Y. Liu +1 more
TL;DR: In this article, a synthetic aperture radar system (SAR) having a range correlator (10) is provided with a hybrid azimuth correlator(12) for correlation utilizing a block-pipelined Fast Fourier Transform (12a) with delay elements (Z) for so delaying SAR range correlated data as to embed in the Fourier transform operation a corner-turning function as the range correlated SAR data is converted from the time domain to a frequency domain.
Patent
Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and ofdm receiver and transmitter
Yuji Nakai,Akihiro Furuta +1 more
TL;DR: In this paper, the fast Fourier transform is performed on a symbol stored in a random access memory (RAM) by a butterfly operation unit in accordance with a RAM address generated by RAM address generator.
Patent
Superresolution image enhancement for a SIMD array processor
TL;DR: In this article, a combination of image magnification and/or image zoom, superresolution processing techniques, and a parallel (SIMD) machine implementation achieve image enhancement and resolution that are better than diffraction-limited image enhancement.