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Patent

Apparatus for detecting and recovering from data destruction caused in an unaccessed memory cell by read, and method therefor

TLDR
In this paper, the memory controller is configured to count how many times data read processing has been executed in memory cells within the management area; read, when the data read-processing count that is counted for a first management area exceeds a first threshold, data and an error correction code that are stored in the memory cells contained within the first management areas; decode the read error correction codes; and write the data corrected by decoding the erasure code in other management areas than the first manager area.
Abstract
Read error in a flash memory destroys data that is not requested to be read, and an efficient read disturb check method is therefore needed. In addition, data may be destroyed beyond repair by error correction before a read error check is run. A non-volatile data storage apparatus including a plurality of memory cells and a memory controller, in which the memory controller is configured to: count how many times data read processing has been executed in memory cells within the management area; read, when the data read processing count that is counted for a first management area exceeds a first threshold, data and an error correction code that are stored in the memory cells within the first management area; decode the read error correction code; and write the data corrected by decoding the error correction code in other management areas than the first management area.

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Citations
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Patent

Efficient Reduction of Read Disturb Errors in NAND FLASH Memory

TL;DR: In this paper, a controller is configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased.
Patent

Memory system and method of accessing a semiconductor memory device

TL;DR: In this article, a memory system is provided with a processor, a main memory, and a flash memory, which includes a non-volatile memory device and a controller configured to drive a control program to control the nonvolatile device.
Patent

RAID configuration in a flash memory data storage device

TL;DR: In this paper, a method of storing data in a flash memory data storage device that includes a plurality of memory chips is described, where first data is written to the first partition while reading data from the second partition.
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Garbage collection for failure prediction and repartitioning

TL;DR: In this article, a method of formatting a data storage device that includes a plurality of flash memory chips includes monitoring a failure rate of memory blocks of one or more memory chips of a storage device.
Patent

Read disturb effect determination

TL;DR: In this paper, the controller is coupled to the nonvolatile memory and configured to accumulate a read disturb count for a first region of the non-volatile RAM, and accumulate error statistics for a second region of RAM, in response to determining that the first region has reached the read disturb limit, relocate at least some data of the first regions.
References
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Patent

Multi-bit-per-cell flash EEPROM memory with refresh

TL;DR: In this article, a multibit per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges correspond to forbidden zones indicating a data error.
Book

Data Handling

Alan Graham, +1 more
Patent

Variable sector-count ecc

TL;DR: In this article, improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code.
Patent

Error correcting code predication system and method

Tony Yoon, +1 more
TL;DR: In memory devices that degrade with use, a memory controller may monitor and record a usage history of portions of the memory. as mentioned in this paper The memory controller can then vary a strength of error correction coding to protect information written to various portions of memory having different usage histories.
Patent

Data storage system

TL;DR: In this article, the first memory cell of the first page is erased, and error-corrected data is written when the determination is “1” or “0”.