Journal ArticleDOI
Area-time optimal VLSI networks for multiplying matrices
About:
This article is published in Information Processing Letters.The article was published on 1980-10-20. It has received 64 citations till now. The article focuses on the topics: Matrix multiplication & Very-large-scale integration.read more
Citations
More filters
Book
The design and analysis of parallel algorithms
TL;DR: Kurskod av teknisk-naturvetenskapliga fakultetsnämnden Kursplan giltig från: 2012, vecka 10 Ansvarig enhet: Inst för datavetenskap SCB-ämnesrubrik: Informatik/Dataoch systemvetenskapskap Huvudområden och successiv fördjupning.
Book
Models of Computation: Exploring the Power of Computing
TL;DR: In Models of Computation, John Savage re-examines theoretical computer science, offering a fresh approach that gives priority to resource tradeoffs and complexity classifications over the structure of machines and their relationships to languages.
Book
Communication Complexity and Parallel Computing
TL;DR: This book is written as a textbook for undergraduate and graduate students and provides a careful explanation of the subject as well as motivation for further research.
Journal ArticleDOI
The VLSI Complexity of Sorting
TL;DR: The area-time complexity of sorting is analyzed under an updated model of VLSI computation, which makes a distinction between "processing" circuits and "memory" circuits; the latter are less important since they are denser and consume less power.
Journal ArticleDOI
New lower bound techniques for VLSI
TL;DR: This paper uses crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks.
References
More filters
Book
A complexity theory for VLSI
TL;DR: A "VLSI model of computation" is developed and upper and lower bounds on the silicon area and time required to solve the problems of sorting and discrete Fourier transformation are derived.
Journal ArticleDOI
The Area-Time Complexity of Binary Multiplication
TL;DR: By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, it is shown that A T 2.0 is shown to be the time required to perform multtphcaUon of n-bit binary numbers on a chip.