Asynchronous NoC Router Design
TLDR
An asynchronous NoC router, for use in 2-D mesh-connected networks, based on the Speed Independent State Transition Graph model, and its performance is compared with a synchronous router of the same functionality.Abstract:
The Quality of Service Network on Chip (QNoC) is the most perferment solution that
provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study
presents an asynchronous NoC router, for use in 2-D mesh-connected networks. It comprises multiple
interconnected input and output ports and dynamic arbitration mechanisms that resolve any output port
conflicts based on the messages priorities. The proposed router protocol and its asynchronous
modeling are based on the Speed Independent State Transition Graph (STG) model. The generated
STG are transformed into VHDL data flow descriptions and the low level implementation is based
onto a parameterized library. This library integrates the popular asynchronous SI modules such as
C-element, Q-element, fairly arbiter, etc. The device is implemented in 0.35 µm CMOS technology and its performance is compared with a synchronous router of the same functionality. The asynchronous router enables a higher data rate and a comparable silicon area.read more
Citations
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Proceedings ArticleDOI
Network interface sharing for SoCs based NoC
TL;DR: Experimental results show that adaptability, FIFO sharing, and gated clock aspects integrated in the proposed NI allow a significant reduction in terms of area and power.
Book ChapterDOI
3D(Dimensional)—Wired and Wireless Network-on-Chip (NoC)
TL;DR: This chapter has discussed about 3D integrated circuits, 3D wired and wireless NoC, Emerging Technologies, and Literature Survey.
Proceedings ArticleDOI
A Quality of Service Network on Chip based on a new priority arbitration mechanism
TL;DR: This paper presents the design of a new on chip network with Quality-of Service (QoS) support, using new dynamic arbitration architecture with a priority-based scheduler to differentiate between multiple packets with various QoS requirements.
Patent
A mimo-ofdm system for robust and efficient neuromorphic inter-device communication
Deying Zhang,Narayan Srinivasa +1 more
TL;DR: In this article, a multiple input multiple output (MIMO) orthogonal frequency division multiplexing (OFDM) system for inter-device communication is described, where information data from each neuromorphic chip is coded and modulated, on the basis of destination, into different channels.
Proceedings ArticleDOI
New generic GALS NoC architectures with multiple QoS
TL;DR: Two generic globally asynchronous locally synchronous (GALS) NoC architectures called GHXPolygon and GHXSpidergon are presented, inspired respectively from the GeNOC and Octagon NoC of TIMA laboratory, and the Spidergon called also STNoC, of STMicroelectronics.