The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

/pdf/a-survey-of-research-and-practices-of-network-on-chip-2rc0mlsrfq.pdf

A survey of research and practices of Network-on-chip

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Design Of Analog Cmos Integrated Circuits

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

https://www.cs.ru.nl/F.Vaandrager/PV/PAPERS/HERMES-ELSEVIER.pdf

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the "design crisis " (gap between silicon technology and actual SoC design capacity) and reduce the time to market. Important issues in MPSoC design are the communication infrastructure and task mapping. MPSoCs may employ NoCs to integrate multiple programmable processor cores, specialized memories, and other IPs in a scalable way. Applications running in MPSoCs execute a varying number of tasks simultaneously, and their number may exceed the available resources, requiring task mapping to be executed at runtime to meet real-time constraints. Most works in the literature present static MPSoC mapping solutions. Static mapping defines a fixed placement and scheduling, not appropriate for dynamic workloads. Task migration has also been proposed for use in MPSoCs, with the goal to relocate tasks when performance bottlenecks are identified. This work investigates the performance of mapping heuristics in NoC-based MPSoCs with dynamic workloads, targeting NoC congestion minimization, a key cost function to optimize the NoC performance. Here, tasks are mapped on the fly, according to communication requests and the load in the NoC links. Results show execution time and congestion reduction when congestion-aware mapping heuristics are employed.

/pdf/heuristics-for-dynamic-task-mapping-in-noc-based-5ck41xfyve.pdf

Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.

Dynamic Task Mapping for MPSoCs

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models

/pdf/a-scalable-test-strategy-for-network-on-chip-routers-31cpumzits.pdf

A scalable test strategy for network-on-chip routers

Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8 times 8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation

Fernando Moraes

Papers

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

Dynamic Task Mapping for MPSoCs

A scalable test strategy for network-on-chip routers

Virtual channels in networks on chip: implementation and evaluation on hermes NoC