Proceedings ArticleDOI
Building Hardware Security Primitives Using Scan-based Design-for-Testability
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TLDR
A comprehensive review of the recent proposals on how scan chain design can present its versatility as security primitives in different areas of hardware security can be found in this article , where the authors elaborate its usage in hardware intellectual property watermarking, fingerprinting and metering, as well as in the design of physical unclonable functions and counterfeit detection.Abstract:
Scan chain is typically used to provide test engineers with complete controllability and observability to the circuit under test to reduce the complexity of VLSI testing. However, it should not be dismissed as just a one-hit-wonder that merely facilitates the test of digital circuits. This study presents a comprehensive review of the recent proposals on how scan chain design can present its versatility as security primitives in different areas of hardware security. More specifically, we elaborate its usage in hardware intellectual property watermarking, fingerprinting, and metering, as well as in the design of physical unclonable functions and counterfeit detection. We analyze the challenges and opportunities in building hardware security primitives using modern scan-based design-for-testability (DfT). read more
References
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Book ChapterDOI
Security Based on Physical Unclonability and Disorder
TL;DR: This chapter provides a classification for past and ongoing work in physical disorder based security alongside with security analyses and implementation examples and outlines some open problems and future research opportunities.
Proceedings ArticleDOI
Hardware metering
Farinaz Koushanfar,Gang Qu +1 more
TL;DR: This work introduces the first hardware metering scheme that enables reliable low overhead proofs for the number of manufactured parts and establishes the connection between the requirements for hardware and synthesis process.
Journal ArticleDOI
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting
TL;DR: This paper presents a finite-state machine (FSM) reengineering method that enhances the FSM synthesis by reconstructing a functionally equivalent but topologically different FSM based on the optimization objective, and it maintains the quality of the synthesis solutions.
Journal ArticleDOI
Testing-Based Watermarking Techniques for Intellectual-Property Identification in SOC Design
TL;DR: A novel testing-based watermarking scheme for intellectual-property (IP) identification that adopts current main system-on-a-chip (SOC) design-for-test (DFT) strategies and solves the IP-identification problem.
Journal ArticleDOI
Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection
Aijiao Cui,Gang Qu,Yan Zhang +2 more
TL;DR: An ultra-low overhead watermarking scheme to protect hard IPs, the dominating form of commercial IPs is proposed and Experimental results validate that the performance overhead is negligible and the watermark is resilient to various possible attacks.