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Patent

Bus structure for overlapped data transfer

James H. Thomas, +2 more
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TLDR
In this paper, an improved system bus structure for versatile use in various digital computer architecture configurations, particularly those of mini-supercomputers, and, designed to support high speed, high reliability, parallel processing of bi-directional signal transfers in a multi-port and multiple central processor unit (CPU) communication environment as between system bus units or devices.
Abstract: 
An improved system bus structure for versatile use in various digital computer architecture configurations, particularly those of mini-supercomputers, and, designed to support high speed, high reliability, parallel processing of bi-directional signal transfers in a multi-port and multiple central processor unit (CPU) communication environment as between system bus units or devices. The system bus structure may be sized for a compact encasement and may carry as many as 129 simultaneous signals to and from various units connected to it. The system bus structure includes enabling structure for a centralized arbitration system, a centralized clock and synchronized transfer system, a centralized transfer monitor, a centralized parity error assessor and signalling system including transfer termination, and, a memory/inter-system inhibit system.

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Method and apparatus for extending a local PCI bus to a remote I/O backplane

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TL;DR: In this article, a method and apparatus for extending a PCI bus interface to a remote I/O backplane through a high speed serial link is presented, providing a large number of slots to alleviate packaging requirements.
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Bus control system

Kondo Nobukazu, +5 more
TL;DR: In this article, a source module initiates a split read access to another module and sends an address of the access destination module and an identifier of the source module to send a response to the source.
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Data recording system buffer management and multiple host interface control

Carl Bonke, +2 more
TL;DR: In this article, a circuit is provided for control and data transfer between a standard data storage device interface and one of a choice of several host computers, using parallel transition memories in conjunction with a buffer memory under common control of a buffer manager.
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Dynamic bus arbitration with concurrent same bus granting every cycle

Marenin George Bohoslaw
TL;DR: In this paper, the authors present an approach and method for optimizing bus arbitration during direct memory access (DMA) data transfers across a nondedicated bus between a memory and/or a plurality of external devices each master having an arbitration priority.
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Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces

Thomas F. Heil, +7 more
TL;DR: In this article, the authors define decoupled bus systems for the multiple processor systems of the present invention, where the main memory for the systems is made up of at least two memory interleaves each of which can be simultaneously accessed through the system buses.
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Patent

System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking

James E. Vander Mey
TL;DR: In this article, a system for resolving conflicts among processors for access to a memory to which the processors are connected by a first bus includes a number of logic circuits, one for each processor.
Patent

Shared direct memory access controller

Nicholas Derchak
TL;DR: In this paper, a shared direct memory access controller between the memory and the subsystem device controller is described, which is used for data transfer between a microprocessor and a set of peripheral devices.
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Data processing system

Yamada H
TL;DR: In this paper, a bus control unit is provided for delivering a "who" signal (which is used for detecting a requesting unit) to the first one of said serially connected data processing units when said unit requests the use of said bus assembly.
Patent

Common bus communication system in which the width of the address field is greater than the number of lines on the bus

David Cureton Baker, +2 more
TL;DR: In this paper, the authors propose a technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system, where the width of the address field is greater than the number of lines on the bus.
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Eight bit standard connector bus for sixteen bit microcomputer using mirrored memory boards

Robert W. Schmidt
TL;DR: In this article, an arrangement of mirror image pairs of memory boards is provided to cross-connect the Data In lines and Data Out lines for one memory board compared to another, these two memory boards being accessed by the same address.