Patent
Cache memory exchange optimized memory organization for a computer system
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TLDR
In this paper, data mapping requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the "victim" data in that CPUs cache must be rewritten.Abstract:
Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping "fill" requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the "victim" data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the `ships crossing in the night` problem is avoided.read more
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Data storage system
Don Harschadath Wanigasekara-Mohotti,Donald M. Craig,Alexandru Mitaru,Christopher Davis,John Howe +4 more
TL;DR: In this article, the authors describe a distributed file system with metadata server machines, content server machines and a client machine, where the content server machine stores slices of the files at locations indicated by the metadata, and the metadata server is used to hide complexity of the system from a number of client machine users.
Patent
Shared bypass bus structure
TL;DR: In this paper, a shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch is proposed, which permits data transfer between the coherent interconnect ports and the co-herency control structures while bypassing the crossbar interface.
Patent
Apparatus and method for a cache coherent shared memory multiprocessing system
TL;DR: In this paper, the authors present a cache-coherent shared-memory multiprocessing system with a flow control unit (FCU) controlling the exchange of data between each device in the system.
Patent
Memory interface and method of interfacing between functional entities
TL;DR: In this paper, a data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core is presented.
Patent
Mechanism for resolving ambiguous invalidates in a computer system
TL;DR: In this article, a system and method for resolving ambiguous invalidate messages received by an entity of a computer system is presented, which is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is waiting to receive.
References
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Patent
Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system
Satyanarayana Nishtala,Zahir Ebrahim,William C. Van Loo,Paul N. Loewenstein,Sue K. Lee,Louis F. Coffin +5 more
TL;DR: In this paper, a multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller, each of which includes a master interface having master classes for sending memory transaction requests to the system controller.
Patent
Parallel processing computer system having shared coherent memory and interconnections utilizing separate undirectional request and response lines for direct communication or using crossbar switching device
TL;DR: In this article, a shared multiprocessing system with several nodes, or processing units, interconnected together for communication purposes by a dual channeled crossbar switch is described, where the interconnection between crossbars is accomplished by a circular ring.
Patent
Crossbar switch for multi-processor, multi-memory system for resolving port and bank contention through the use of aligners, routers, and serializers
TL;DR: In this paper, a self-routing crossbar switch (SRBS) is defined, where a processor is attached to each input port and a memory module is connected to each output port; each of the N processors can transmit a memory request simultaneously provided that there is no port contention and no bank contention.
Patent
Cache memory control method and apparatus, and method and apparatus for controlling memory capable of interleave control
TL;DR: In this article, a memory control system for performing interleave access or non-interleave access to an information memory medium having a plurality of banks of different capacities is presented, and a boundary address indicative of a boundary between the interleave and non-Interleave access areas is compared with an access address to the information memory.
Patent
A multi-processor system with shared memory
TL;DR: A multi-processor system in which a plurality of processors have access to shared memory modules, comprising a memory control unit, interconnection logic circuits, a system bus for the multipoint connection of the processors to the memory control units and for the transfer of memory addresses and commands for ordered and successive read/write operations via the system bus and the memory controller unit, is described in this article.