Patent
Cached random access memory device and system
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TLDR
In this article, the authors proposed an approach to reduce access time to RAM arrays, especially DRAMs, by including fast access cache rows, e.g., four rows, to store data from accessed rows of the array, where data can then be accessed without precharging, row decoding sensing, and other cycling usually required to access the DRAM.Abstract:
A device for reducing access time to RAM arrays, especially DRAMs, by including fast access cache rows, e.g., four rows, to store data from accessed rows of the array, where data can then be accessed without precharging, row decoding sensing, and other cycling usually required to access the DRAM. Address registers, comparators, and MRU/LRU register and other cache control logic may be included in the device. The device allows parallel transfer of data between the RAM array and the cache rows. The device may be constructed on a single chip. A system is disclosed which makes use of the cache RAM features in a data processing system to take advantage of the attributes of a cache RAM memory.read more
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Patent
Distributed, on-chip cache
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