Patent
Caching system and method for a network storage system
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TLDR
In this paper, a cache system and method in accordance with the invention includes a cache near the target devices and another cache at the requesting host side so that the data traffic across the computer network is reduced.Abstract:
A cache system and method in accordance with the invention includes a cache near the target devices and another cache at the requesting host side so that the data traffic across the computer network is reduced. A cache updating and invalidation method are described.read more
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References
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Patent
System for accessing distributed data cache channel at each network node to pass requests and data
TL;DR: In this paper, the authors propose a data conduit that provides an active virtual circuit (AVC) from the NDC client site (24) through intermediate NDC sites (26B, 26A, and 26B) to the server site (22).
Patent
Performance optimizations for computer networks using http
TL;DR: In this paper, a connection cache is maintained by an agent on the network access equipment (254) to more quickly respond to request for network connections to the server (256), and the agent may maintian a cache of information to more frequently respond to requests to get an object if it has been modified.
Patent
Remote file services network-infrastructure cache
TL;DR: The NI Cache as discussed by the authors is a network infrastructure cache that provides proxy file services to a plurality of client workstations concurrently requesting access to file data stored on a server through a network interface.
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User name authentication for gateway clients accessing a proxy cache server
TL;DR: In this paper, a system and method for regulating access to a proxy cache server residing on an institutional intranet or local network provides a directory for storing user names that are appended to client requests for remote web site information.
Patent
Hierarchical cache memory system and method
Wilson Andrew W,Frank Steven J +1 more
TL;DR: In this paper, the authors propose a cache coherency management scheme for a shared bus multiprocessor which includes several processors each having its own private cache memory, each private cache is connected to a first bus to which a second, higher level cache memory is also connected.