Patent
Circuit testing apparatus
Mitsuhiko Ezoe,Hiroshige Ozawa +1 more
TLDR
In this paper, the presence of a non-coincidence signal is represented by binary digits and stored in a shift register, where the stored bits are translated into information indicating the location of a circuit trouble.Abstract:
Circuit testing apparatus includes a pulse oscillator providing clock pulses, a binary counter for counting the clock pulses to successively generate binary numbers, and a translator which translates the successive binary numbers into a series of test patterns. The test patterns include a series of input bit patterns used to energize the input leads of an electronic logic circuit under test and a series of output binary digits, each of which corresponds to the respective one of the input patterns. Each of the binary digits is compared with an output from the logic circuit under test. When the circuit tested is not functioning as prescribed for a particular set of input pattern, a noncoincidence signal will be produced to disable the binary counter in order to permit the test operator to register the test mode in which the trouble occurred. The binary counter may be enabled manually after registration to complete the prescribed number of tests. The presence of a noncoincidence signal is represented by binary digits and stored in a shift register. The stored bits are translated into information indicating the location of a circuit trouble, if any.read more
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References
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Patent
Method of propagation delay testing a functional logic system
TL;DR: Propagation delay testing is performed on a generalized and modular logic system that is utilized as an arithmetic/logical unit in a digital computer as discussed by the authors, where the propagation paths through the system circuitry are sensitized by test patterns from an automatic test generator.
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Method and apparatus for testing high circuit density devices
TL;DR: In this article, the authors present an approach and method for testing complex electronic circuitry including in particular solid state semiconductor devices, which is accomplished by varying the values of the ''''ones'' and '''''zeros'' of a test pattern impressed on the device under test.
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Fault testing of logic circuits
TL;DR: In this article, a method and apparatus for detecting faults in logic circuits requires the retention of a single binary reference word for each circuit type to be tested, which is characteristic of a properly functioning circuit of the same type.