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Patent

Clock recovering apparatus and method

Willard J. Torgrim
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TLDR
In this paper, an internal actuated counter is used to generate a lower frequency data clock and reset to an initial condition whenever the incoming data phase deviates mote than a prescribed amount from the phase of generated clock.
Abstract: 
A circuit for generating a clock based on time of receipt of a RZ (return to zero) data bit stream using a known clocking frequency. An internal actuated counter is used to generate a lower frequency data clock and is reset to an initial condition whenever the incoming data phase deviates mote than a prescribed amount from the phase of the generated clock. A non-zero data pattern is required to periodically resynchronize the derived clock with the incoming data.

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Patent

Digital timing recovery system

Glen D. Rattlingourd
TL;DR: In this paper, the clock reference signal is phase matched with the digital data by comparing the positive going and negative going edges of the data with the clocking edge of the clock signal.
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Asynchronous data clock generator

Richard G. Cease, +2 more
TL;DR: In this paper, a circuit and method for generating a substantially smooth clock for clocking asynchronous data to a user device is presented, where incoming asynchronous data is stored in an elastic buffer such as a first-in first-out memory.
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Metastable prevent circuit

Edward L. Grivna
TL;DR: A metastable prevent circuit comprises a plurality of parallel channels, each coupled to receive and synchronize asynchronous pulses to a synchronous clock signal, and a shift register is responsive to the asynchronous pulses.
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Phase lock loop preconditioning circuit

Robert Kirk Moulton, +1 more
TL;DR: In this paper, a preconditioning circuit is inserted in series between a coded stream of data pulses and a standard commercially available phase lock loop of the type having a nonharmonic phase detector.
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Clock phasing circuit

Bill H. Niemi, +2 more
TL;DR: A clock phasing circuit for aligning data which is transmitted by a first clock, running at a particular frequency, with a second clock running at the same frequency as the first clock but in a different and undetermined phase relationship is described in this article.