Patent
CMOS Schmitt trigger and oscillator
TLDR
In this paper, a CMOS Schmitt trigger circuit displays a lower trigger point that is one N channel transistor threshold above the negative power supply potential and an upper trigger point, which is one P channel threshold below the positive power supply maximum potential.Abstract:
A CMOS Schmitt trigger circuit displays a lower trigger point that is one N channel transistor threshold above the negative power supply potential and an upper trigger point that is one P channel transistor threshold below the positive power supply potential. Thus, the circuit hysteresis loop is related to supply potential and device threshold values. When the trigger circuit is employed in a relaxation oscillator configuration, the oscillator frequency is independent of power supply voltage and manufacturing variables in the CMOS process that vary transistor threshold values.read more
Citations
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Low power three-stage CMOS input buffer with controlled switching
TL;DR: In this article, a CMOS low power Schmitt type input buffer for a dynamic random access memory (DRAM) circuit is characterized. And the buffer is further characterized in that a falling edge has better than average noise immunity and has a slightly longer propagation time through the buffer than a rising edge.
Patent
Schmitt trigger circuit using MOS transistors and having constant threshold voltages
TL;DR: In this paper, an input CMOS inverter comprises a complementary pair of first and second MOS transistors having their gates connected together to receive an input signal, and a buffer circuit connected between drains of the first and Second MOS Transistors.
Patent
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TL;DR: A CMOS Schmitt trigger circuit responsive to TTL logic levels is described in this paper, and a supply regulator circuit renders the circuit independent of temperature, supply voltage and device parameters.
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TL;DR: In this paper, a transfer gate of CMOS structure is connected between the gates of the CMOS transistors as a resistive element, which reduces the changes in the gate potentials of output transistors.
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Signal driver circuit operable to control signal rise and fall times
TL;DR: In this article, a signal driver circuit (10) is provided that comprises a first inverter comprising a P-FET (14), an N-FCET (16), and a resistor (18).
References
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Patent
CMOS Schmitt trigger
TL;DR: In this article, the input of the Schmitt trigger is applied in parallel to the gates of a plurality of stacked MOS transistors, and the output hysteresis signal is inverted and a portion of the inverted output signal is fed back via a second inverter to the output node for stabilizing the output signal.
Patent
Set-reset flip-flop
TL;DR: In this paper, a set-reset circuit comprised of a master flip-flop coupled to a slave flipflop by a transmission fate is presented. But the set-set circuit is limited to a single master and a single slave.
Patent
CMOS voltage controlled oscillator
TL;DR: In this paper, a CMOS voltage controlled oscillator is described, which is a linear CMOS circuit and exhibits an infinite current gain, a near infinite input impedance, a very high voltage gain with a corresponding low power consumption.
Patent
Memory cell and array
TL;DR: In this paper, an active storage or memory cell includes first and second high input impedance inverters cross coupled to form a flip-flop and the output of the second inverter is significantly lower than the output impedance of the first inverter.
Patent
Bisitable digital circuitry
TL;DR: In this paper, a cross-coupled gate with complementary inputs provided by CMOS threshold circuits coupled to a common digital signal input is presented. But the coupling between gates maintains the bistable digital circuits in a given stable state until the high and low threshold voltages are crossed over.