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Cost and performance of VLSI computing structures

M. Rem, +1 more
- pp 196-203
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TLDR
In this paper, the area-time product is used as a cost function for the design of a RAM-based system and an associative system, and it is shown that in each case an optimum design is possible using the area time product.
Abstract
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolithic silicon chip. Conducting paths are required for communicating information throughout any integrated system. The length and organization of these communication paths place a lower bound on the area and time required for system operations. Optimal designs can be achieved in only a few of the many alternative structures. Two illustrative systems are analyzed in detail: a RAM-based system and an associative system. It is shown that in each case an optimum design is possible using the area-time product as a cost function.

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Citations
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Book

A complexity theory for VLSI

TL;DR: A "VLSI model of computation" is developed and upper and lower bounds on the silicon area and time required to solve the problems of sorting and discrete Fourier transformation are derived.
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Models of Computation: Exploring the Power of Computing

TL;DR: In Models of Computation, John Savage re-examines theoretical computer science, offering a fresh approach that gives priority to resource tradeoffs and complexity classifications over the structure of machines and their relationships to languages.
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Let's Design Algorithms for VLSI Systems

H. T. Kung
TL;DR: Examples of algorithms that are suitable for VLSI implementation are given, a taxonomy for algorithms based on their communication structures is provided, and some of the insights that are beginning to emerge from efforts in designing algorithms for V LSI systems are discussed.
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Direct VLSI Implementation of Combinatorial Algorithms

TL;DR: New algorithms for dynamic programming and transtivc closure are presented which are appropriate for very large-scale integration implementation and are shown to be suitable for dynamic integration implementation.
Journal ArticleDOI

The Area-Time Complexity of Binary Multiplication

TL;DR: By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, it is shown that A T 2.0 is shown to be the time required to perform multtphcaUon of n-bit binary numbers on a chip.