Proceedings ArticleDOI
Cost Minimization of Partitions into Multiple Devices
Roman Kužnar,Franc Brglez,Krzysztof Kozminski +2 more
- pp 315-320
Reads0
Chats0
TLDR
A multi-way partitioning algorithm based on a recursive application of the Fiduccia-Mattheyses bipartitioning heuristic, extended to handle the overall goal of the cost minimization and the constraints reflecting the limitations on the capacity of FPGA chips is proposed.Abstract:
This paper considers the problem of obtaining a minimum-cost partitioning of a large logic circuit into a collection of subcircuits implementable with devices selected from a given library. Each device in the library may have a different price, size, and terminal capacity. We propose a multi-way partitioning algorithm based on a recursive application of the Fiduccia-Mattheyses bipartitioning heuristic, extended to handle (a) the overall goal of the cost minimization and (b) the constraints reflecting the limitations on the capacity of FPGA chips. The experimental implementation of the proposed algorithm has exhibited a very encouraging performance, producing solutions close to the theoretical minima calculated for many benchmark circuits.read more
Citations
More filters
Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
The roles of FPGAs in reprogrammable systems
TL;DR: The promise and problems of reprogrammable systems are discussed, including an overview of the chip and system architectures of repprogrammable systems as well as the applications of these systems.
The Roles of FPGA's in Reprogrammable Systems
TL;DR: The promise and problems of reprogrammable systems are discussed, including an overview of the chip and system architectures of repprogrammable systems as well as the applications of these systems.
Proceedings ArticleDOI
The Development of an Operating System for Reconfigurable Computing
G. Wigley,D. Kearney +1 more
TL;DR: Tests on the prototype with benchmark examples show that it is a feasible and that fragmentation of the area of the FPGA among many users is manageable.
Proceedings ArticleDOI
A probability-based approach to VLSI circuit partitioning
Shantanu Dutt,Wenyong Deng +1 more
TL;DR: A probabilistic gain computation approach called PROP is presented that is capable of capturing the global and future implications of moving a node at the current time and is appreciably faster than the above clustering-based techniques, and only a little slower than FM and LA, both of which are very fast.
References
More filters
Proceedings ArticleDOI
A Linear-Time Heuristic for Improving Network Partitions
TL;DR: An iterative mincut heuristic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network.
Proceedings ArticleDOI
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Journal ArticleDOI
Multiple-way network partitioning
TL;DR: A multiple-block network partitions algorithm adapted from a two-block iterative improvement partitioning algorithm and of the level gain concept to multiple blocks seeks to improve the partition uniformly with respect to all blocks as oppose to making repeated uses of two-way partitioning.
Proceedings ArticleDOI
A general purpose multiple way partitioning algorithm
TL;DR: This algorithm incorporates a top-down clustering technique to deal with the local minima problems in common heuristics, a novel multi-pin net model to capture the contributory moves, and a Primal-hal iteration to enhance the iterative improvement.