Proceedings ArticleDOI
Decimal addition in FPGA
Géry Jean Antoine Bioul,Martín Vázquez,Jean-Pierre Deschamps,Gustavo Sutter +3 more
- pp 101-108
TLDR
Results for big operands show that the decimal adder works faster than an equivalent binary implementation and furthermore the coding / decoding processes are no more needed.Abstract:
This paper presents a study of the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGAs. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are then presented with the corresponding time performances and area consumption figures. In order to compare the results, the straight implementation of a decimal ripple-carry adder and the FPGA optimized base 2 adder for the same range are implemented. Results for big operands show that the decimal adder works faster than an equivalent binary implementation and furthermore the coding / decoding processes are no more needed.read more
Citations
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Proceedings ArticleDOI
Fully Redundant Decimal Arithmetic
Saeid Gorgin,Ghassem Jaberipur +1 more
TL;DR: A framework for fully redundant decimal arithmetic, where all operands and results belong to the same redundant decimal number system and can be stored and later used as operands of further decimal operations.
Proceedings ArticleDOI
FPGA Implementations of BCD Multipliers
TL;DR: A variety of algorithms for basic one by one digit multiplication are proposed and FPGA implementations are presented, and time and area results for sequential and combinational implementations show better figures compared with previous published work.
Proceedings ArticleDOI
A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding
Alvaro Vazquez,Elisardo Antelo +1 more
TL;DR: It is shown that the resultant implementations for IEEE 754-2008 Decimal64 and Decimal128 formats reduce significantly the area and latency required for significand BCD addition/subtraction and decimal rounding in previous high-performance decimal floating-point adders.
Proceedings ArticleDOI
Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs
TL;DR: A combinational implementation maps quite well into the slice structure of the Xilinx Virtex-5/Virtex-6 families and it is highly pipelineable and outperforms the area and latency figures of previous implementations in FPGAs.
Proceedings ArticleDOI
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations
TL;DR: FPGA implementations of add/subtract algorithms for 10´s complement BCD numbers for carry-chain optimization purposes on 6-input LUT´s Xilinx Virtex-5 FPGA technologies are presented.
References
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Proceedings ArticleDOI
Decimal floating-point: algorism for computers
TL;DR: This work introduces a new approach to decimal floating point which not only provides the strict results which are necessary for commercial applications but also meets the constraints and requirements of the IEEE 854 standard.
Book
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
TL;DR: The author's research focused on the development of a number representation system that allowed for the addition and subtraction of numbers up to and including the number of bits in a discrete-time system.
Proceedings ArticleDOI
The IBM z900 decimal arithmetic unit
TL;DR: This paper details the decimal arithmetic engine in the recently announced z900 microprocessor, which is supported in many software languages but not yet available on many microprocessors.
Journal ArticleDOI
Binary-coded decimal digit multipliers
Ghassem Jaberipur,Amir Kaivani +1 more
TL;DR: A novel design is provided for the BCD-digit multiplier, which can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism, in semi- and fully parallel hardware decimal multiplication units.