PatentDOI
Defect isolation using scan-path testing and electron beam probing in multi-level high density asics
Grant Lindberg,Sharad Prasad,Kaushik De,Arun Gunda +3 more
- Vol. 2334, pp 272-279
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TLDR
A successful method of defect isolation using scan-path testing in conjunction with electron beam probing for isolating various defects on devices with multi-layer (3+) metallization, 500 K usable gates and 2000 scan elements is presented.Abstract:
A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).read more
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References
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Test generation by environment emulation
TL;DR: In this article, a test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit, which is used for device testing by comparing its outputs to those of a logic circuit and injecting selected faults to aid in device debug.
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Method of and apparatus for automatic fault diagnosis of electrical circuits employing on-line simulation of faults in such circuits during diagnosis
TL;DR: In this article, the use of on-line simulation of circuit faults during diagnosis to generate a small part of a complete fault dictionary needed for diagnosis of the circuit, being adapted for use of a mini-computer-based automated test system having only a small amount of secondary storage; and a heuristic approach for a partial match of faulty behaviour that leads to a highly probable diagnosis.
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Method for designing a scan path for a logic circuit and testing of the same
TL;DR: In this paper, a scan path is designed to connect flip-flops in a logic circuit and test patterns are created by the circuit designer to determine potential faults in the circuit which are not detected by the patterns and not observable at any flipflop.
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Robert G. Wehling,David C. Davis,Richard J Walsh,Allen L Clarke,Rossel H Bowen,Gilbert Walter E,Glover Wayne L +6 more
TL;DR: An automatic printed circuit board tester to test printed circuit boards and diagnose faults in digital and analog elect-rical circuit networks is disclosed in this paper, which is comprised of control, stimuli, and interconnection networks in combina-tion with measuring instrumentation.
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TL;DR: In this article, a method is described which increases the diagnostic resolution of a fault dictionary 130 used by automated test equipment (ATE) to determine a failed device in a unit under test 120.