Proceedings ArticleDOI
Design & analysis of 16 bit RISC processor using low power pipelining
Priyanka Trivedi,Rajan Prasad Tripathi +1 more
- pp 1294-1297
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TLDR
A 16 bit low power pipelined RISC processor is proposed by us in this paper, the RISC Processor consists of the block mainly ALU, Universal shift register and Barrel Shifter.Abstract:
A 16 bit low power pipelined RISC processor is proposed by us in this paper, the RISC processor consists of the block mainly ALU, Universal shift register and Barrel Shifter. We have used modified Harvard architecture that uses separate memories for its instruction & data memory response where as in the other architecture by von Neumann, has only one shared memory for instruction and data, with one data bus and address bus with between data memory & processor memory. The remedial architectural modification has been made in incremental circuit utilized in carry select adder unit of the ALU in the RISC Processor. Operation in the core RISC Processor Fetch, Decode, execute, write back is implemented in the 2 stage pipelining with the positive edge & negative Edge. The process has been realized using XILINX ISE Design suit 13.2 & the Dynamic power is minimized in the RISC Core through the clock gating technique that is an efficient power technique and the total power estimation is done by the X Power analyzer. All the implementation is done in XILINX KINTEX XC7K1607-3fbg676 in it kit 28 nm technology are used. The simulation illustrate the total power dissipated by the processor to be 0.220 watt, and the Latency is 1.5 cycle.read more
Citations
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Design and Analysis of A 32-bit Pipelined MIPS Risc Processor
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8-bit softcore microprocessor with dual accumulator designed to be used in FPGA
TL;DR: The designed architecture is composed by two accumulators, which can be used either as source or destination for the operation of the ALU, and gives some flexibility to the design, doing it better than a single-accumulator processor, and getting it closer to the register-based processors.
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Designing of 32-Bit Configurable Hack CPU On FPGA
Ruchita Kawle,Shubhada Thakare +1 more
TL;DR: In this paper, the authors discuss the previous research on various 16-bit, 32-bit RISC processors with its architecture and high-speed with minimal energy consumption and find that the pipeline has five stages and number of instructions has been created for such processors.
Proceedings ArticleDOI
An Optimum Design and Implementation of a 16-bit ALU on CADENCE Using RISC-V Architecture
TL;DR: In this paper , the authors developed an optimum design of a 16-bit RISC-V-based arithmetic logic unit using CADENCE tool in the EDA Playground along with XILINX ISE Design Suite 14.7.
Proceedings ArticleDOI
Design and Implementation of Five Stages Piplined RISC Processor on FPGA
TL;DR: In this article , a processor with a five-stage pipeline for educational purposes is proposed, which can execute five 16-bit instructions simultaneously and is designed and simulated using Verilog HDL.
References
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Journal ArticleDOI
Low-Power and Area-Efficient Carry Select Adder
B. Ramkumar,Harish M. Kittur +1 more
TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.
Journal ArticleDOI
DCG: deterministic clock-gating for low-power microprocessor design
TL;DR: A deterministic clock-gating (DCG) technique which effectively reduces clock power in high-performance processors by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers.
Proceedings ArticleDOI
16-Bit RISC processor design for convolution application
TL;DR: The utility of the RISC processor is extended towards convolution application, one of the most important signal processing application, and the total dissipated power by the processor is depicted to be approximately 329.3 μW.
Design and Performance Analysis of 8-bit RISC Processor using Xilinx Tool
TL;DR: The main objective of this paper is to design and implement an 8-bit Reduced Instruction Set (RISC) processor using XILINX Spartan 3E tool and the enhanced feature of Spartan-3E deliberately reduces the cost per logic cell designed.
Proceedings ArticleDOI
SeSCG: Selective sequential clock gating for ultra-low-power multimedia mobile processor design
TL;DR: A novel selective sequential clock gating (SeSCG) technique is proposed that can choose optimal sequentialClock gating style selectively for ultra-low-power design based on the proposed toggle rate analysis at RT level and the experimental results show that the conventional sequential Clock gating scheme even increases average 4.77% of total power.