Journal ArticleDOI
Detecting I/O and Internal Feedback Bridging Faults
Shiyi Xu,Stephen Y. H. Su +1 more
TLDR
It is shown that only two test patterns are sufficient to detect feedback bridging faults between input and output lines of a general combinational network.Abstract:
The testing of bridging faults (short circuits) has become increasingly important with the increasing density in VLSI (very large scale integration) chips. Yet very little work has been done in this area. In this correspondence, based on a two-state sequential machine model, we present the conditions for a circuit with feedback bridgings to oscillate and to exhibit stable sequential behavior. It is shown that only two test patterns are sufficient to detect feedback bridging faults between input and output lines of a general combinational network. We derive a simple equation to generate test patterns for detecting feedback bridging faults among internal lines of a general combinational network.read more
Citations
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Book
Iddq Testing for CMOS VLSI
TL;DR: Iddq testing has been widely used in the field of semiconductor testing as discussed by the authors and many semiconductor companies now consider Iddq test as an integral part of the overall testing for all IC's.
Proceedings ArticleDOI
An analysis of feedback bridging faults in MOS VLSI
TL;DR: It is shown that when a feedback bridging fault does not cause oscillations, it creates an anomalous output and the authors recommend measurement of power supply current to detect such faults in CMOS circuit.
Proceedings ArticleDOI
Modeling feedback bridging faults with non-zero resistance
TL;DR: The complexity of resistive feedback bridging fault simulation, accurate enough to resolve such situations, will probably be prohibitively high and possible simplifying assumptions are proposed.
Journal ArticleDOI
Modeling Feedback Bridging Faults with Non-Zero Resistance
TL;DR: It is concluded that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and proposed possible simplifying assumptions are proposed.
Journal ArticleDOI
Test generation for cyclic combinational circuits
TL;DR: This work provides, for the first time, a formal analysis of the test generation problem for cyclic combinational circuits, which leads to a clear insight into generation of tests, as well as a classification of untestable faults for such circuits.
References
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Journal ArticleDOI
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
M.J.Y. Williams,J.B. Angell +1 more
TL;DR: With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture.
Journal ArticleDOI
Bridging and Stuck-At Faults
TL;DR: The commonly used stuck-at fault fails to model logic circuit shorts, so Bridging faults are defined to model these circuit mal-functions.
Journal ArticleDOI
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults
Abramovici,Menon +1 more
TL;DR: This approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well, and shows that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.
Proceedings Article
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults.
Journal ArticleDOI
Diagnosis of Short-Circuit Faults in Combinational Circuits
TL;DR: This correspondence considers the problems associated with detection of two other fault models, shorted diode and input Bridge faults, both corresponding to shorts.
Related Papers (5)
Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines
Karpovsky,Su +1 more
Simulation and generation of IDDQ tests for bridging faults in combinational circuits
S. Chakravarty,P.J. Thadikaran +1 more