Patent
Detection of cycle slippage between two signals
Reads0
Chats0
TLDR
In this paper, a cycle slippage condition exists when phase comparisons of the signals indicate the clock output is passing from a phase lag error to a phase lead error without passing through a region of no phase error.Abstract:
Clocking signals are recovered from an incoming signal train by a master clock oscillator phase locked to the incoming signals, and, in the event of a failure or malfunction involving the master clock, by a standby clock similarly phase locked to the incoming signals. One of the malfunctions occurs when the phase of the clock output slips a cycle with respect to the phase of the signal train. It is determined that a cycle slippage condition exists when phase comparisons of the signals indicate the clock output is passing from a phase lag error to a phase lead error, or vice versa, without passing through a region of no phase error.read more
Citations
More filters
Patent
Timing recovery circuit for digital data
TL;DR: In this article, a timing recovery circuit receives a timing component signal and generates a signal having a frequency varying in response to a control signal, which is combined into the control signal that adjusts the frequency of the generated signal into synchronization with the timing component.
Patent
Cycle slip detection using low pass filtering
TL;DR: In this paper, a cycle slip detector and detection method for a phase comparison circuit are provided, which includes a cycle-slide detection filter possessing a predetermined filter bandwidth and a predetermined high frequency cut-off.
Patent
Frequency and phase comparator with slip detection capability
TL;DR: In this paper, a frequency and phase comparator circuit for determining the frequency difference between a reference signal of a known frequency and a variable signal of unknown frequency was proposed. But the phase shifts indicate that at some point in time during transmission, the two signals were out of phase and not of exact frequency.
Patent
Frequency generator with a controlled limit on frequency deviation from a synchronizing frequency
TL;DR: In this article, a digital counter driven by a stable high frequency source generates a periodic signal synchronized to an external signal source, and the external signal is examined during these quantized time intervals for the occurrence of significant cyclic events such as zero crossing.
References
More filters
Patent
Timing wave recovery circuit for synchronous data repeater
Mason A Logan,Henry C Schroeder +1 more
Patent
Delayed clock pulse synchronizing of random input pulses
TL;DR: In this paper, a clock gate allows the counter to accumulate clock pulse count when the input and output states are different and prevents the counter from accumulating clock pulses when the inputs and outputs are the same, thus taking into account fine chatter at the input transitions to extend the 5 millisecond time an amount depending upon the nature and extent of fine chatter.
Patent
Method and apparatus for timing pulse synchronisation
Dao Thua-Liet,Sakic Boris +1 more
TL;DR: In this article, the output of a clock pulse generator is synchronized with incoming binary data on line 12 by adding or deleting a pulse from the divider in accordance with the sense of the phase error.