Patent
Dual call/return stack branch prediction system
G. Henry,Thomas McDonald +1 more
TLDR
In this paper, the authors propose a branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. But their approach requires the microprocessor to decode the instruction before decoding it to know whether it is actually a return instruction.Abstract:
A branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. The apparatus includes a first call/return stack that provides a speculative return address based upon a return instruction hit in a speculative branch target address cache (BTAC) of an instruction cache fetch address prior to decoding of the instruction to know whether it is actually a return instruction. The speculative return address is provided early in the pipeline and the microprocessor speculatively branches to the speculative return address. Later in the pipeline, a second call/return stack provides a non-speculative return address after the instruction is decoded and verified to be a return instruction. A comparator compares the speculative and non-speculative return addresses, and if the two addresses mismatch, the microprocessor branches to the non-speculative return address.read more
Citations
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Patent
Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
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Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
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References
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Proceedings ArticleDOI
A secure and reliable bootstrap architecture
TL;DR: The AEGIS architecture for initializing a computer system validates integrity at each layer transition in the bootstrap process, and it is shown how this results in robust systems.
Patent
High performance, superscalar-based computer system with out-of-order instruction execution
Le Trong Nguyen,Derek J. Lentz,Yoshiyuki Miyayama,Sanjiv Garg,Yasuaki Hagiwara,Johannes Wang,Te-Li Lau,Sze-Shun Wang,Quang H. Trang +8 more
TL;DR: In this paper, a superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput is presented, where the data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
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Patent
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