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Patent

Dual-instruction-set architecture CPU with hidden software emulation mode

James S. Blomgren, +1 more
TLDR
In this paper, a dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computers) code.
Abstract: 
A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode Emulation mode is entered upon reset, and performs various system checks and memory allocation A special emulation driver is loaded into a portion of main memory set aside at reset Software routines to emulate the more complex instructions of the CISC architecture using RISC instructions are also loaded into the emulation memory A TLB is enabled, and translation tables and drivers are set up in the emulation memory All TLB misses, even in the user modes, will cause entry to a translator driver in emulation mode Since the TLB is always enabled for the user modes, and all misses are handled by the emulation code, the emulation code can set aside a portion of memory for itself and insure that the user programs never have access to the emulation memory Thus the programs, including operating systems, in CISC or RISC mode are unaware of emulation memory or even the existence of emulation mode

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Patent

Apparatus for executing programs for a first computer architechture on a computer of a second architechture

John S. Yates, +4 more
TL;DR: In this paper, the authors propose a set of entry exceptions, called entry exception, exit exception, entry handler, and resumption exception, which are cooperatively designed to maintain an association between a thread and an extended context of the thread through context change induced by the operating system.
Patent

Java Virtual Machine hardware for RISC and CISC processors

Mukesh K. Patel, +2 more
TL;DR: In this paper, a hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java bytecodes, and the Java hardware accelerator preferably includes Java bytecode translation into native CPU instructions.
Patent

Recording classification of instructions executed by a computer

John S. Yates, +2 more
TL;DR: In this paper, an instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions.
Patent

Deferred shadowing of segment descriptors in a virtual machine monitor for a segmented computer architecture

Beng-Hong Lim, +2 more
TL;DR: In this paper, the authors propose a shadow descriptor table that stores shadow descriptors for certain VM segment descriptors, which are then shadowed descriptors are compared with their corresponding shadowed VM descriptors and synchronization for the pair of descriptors is established.
Patent

Computer for execution of RISC and CISC instruction sets

Korbin S. Van Dyke, +2 more
TL;DR: In this paper, a computer with a general register file of registers, a RISC instruction decoder, and a CISC decoder is shown to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC Instruction Decoder and the CISC Instruction Decoder.
References
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Book

Structured Computer Organization

Andrew S. Tanenbaum, +1 more
TL;DR: This new edition includes a wealth of new material about modern I/O devices, a detailed discussion of the Java Virtual Machine (including a microprogrammed implementation of a subset of a JVM), extensive coverage of multiprocessing, and much more.
Book

Computer Organization

V. Carl Hamacher, +2 more
TL;DR: The book highlights modern developments in computer design,I/O and performance and presents real system examples from around the world.
Patent

Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations

Robert J. Bullions, +4 more
TL;DR: In this paper, the look aside buffer (TLB) hardware is provided in a central processor that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment.
Patent

Reduced instruction set computing apparatus and methods

Gregory Alan Portanova, +1 more
TL;DR: A reduced instruction set computer (RISC) with a Harvard architecture is described in this paper, where the RISC may be used simply as a RISC or may be designed to emulate a CISC.
Patent

High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions

Robert F. Beckwith, +4 more
TL;DR: In this article, a pipelined central processor capable of executing both single-cycle instructions and multicycle instructions is provided, which includes an instruction cache memory and a prediction cache memory that are commonly addressed by a program counter register.