An intelligent electronic appliance preferably includes a user interface, data input and/or output port, and an intelligent processor. A preferred embodiment comprises a set top box for interacting with broadband media streams, with an adaptive user interface, content-based media processing and/or media metadata processing, and telecommunications integration. An adaptive user interface models the user, by observation, feedback, and/or explicit input, and presents a user interface and/or executes functions based on the user model. A content-based media processing system analyzes media content, for example audio and video, to understand the content, for example to generate content-descriptive metadata. A media metadata processing system operates on locally or remotely generated metadata to process the media in accordance with the metadata, which may be, for example, an electronic program guide, MPEG 7 data, and/or automatically generated format. A set top box preferably includes digital trick play effects, and incorporated digital rights management features.

Intelligent electronic appliance system and method

An adaptive interface for a programmable system, for predicting a desired user function, based on user history, as well as machine internal status and context. The apparatus receives an input from the user and other data. A predicted input is presented for confirmation by the user, and the predictive mechanism is updated based on this feedback. Also provided is a pattern recognition system for a multimedia device, wherein a user input is matched to a video stream on a conceptual basis, allowing inexact programming of a multimedia device. The system analyzes a data stream for correspondence with a data pattern for processing and storage. The data stream is subjected to adaptive pattern recognition to extract features of interest to provide a highly compressed representation which may be efficiently processed to determine correspondence. Applications of the interface and system include a VCR, medical device, vehicle control system, audio device, environmental control system, securities trading terminal, and smart house. The system optionally includes an actuator for effecting the environment of operation, allowing closed-loop feedback operation and automated learning.

Ergonomic man-machine interface incorporating adaptive pattern recognition based control system

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

An adaptive interface for a programmable system, for predicting a desired user function, based on user history, as well as machine internal status and context. The apparatus receives an input from the user and other data. A predicted input is presented for confirmation by the user, and the predictive mechanism is updated based on this feedback. Also provided is a pattern recognition system for a multimedia device, wherein a user input is matched to a video stream on a conceptual basis, allowing inexact programming of a multimedia device. The system analyzes a data stream for correspondence with a data pattern for processing and storage. The data stream is subjected to adaptive pattern recognition to extract features of interest to provide a highly compressed representation that may be efficiently processed to determine correspondence. Applications of the interface and system include a video cassette recorder (VCR), medical device, vehicle control system, audio device, environmental control system, securities trading terminal, and smart house. The system optionally includes an actuator for effecting the environment of operation, allowing closed-loop feedback operation and automated learning.

Adaptive pattern recognition based control system and method

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Design Of Analog Cmos Integrated Circuits

A pipelined central processor capable of executing both single-cycle instructions and multicycle instructions is provided. An instruction fetch stage of the processor includes an instruction cache memory and a prediction cache memory that are commonly addressed by a program counter register. The instruction cache memory stores instructions of a program being executed and microinstructions of a multicycle instruction interpreter. The prediction cache memory stores interpreter call predictions and interpreter entry addresses at the addresses of the multicycle intructions. When a call prediction occurs, the entry address of the instruction interpreter is loaded into the program counter register on the processing cycle immediately following the call prediction, and a return address is pushed onto a stack. The microinstructions of the interpreter are fetched sequentially from the instruction cache memory. When the interpreter is completed, the prediction cache memory makes a return prediction. The return address is transferred from the stack to the program counter register on the processing cycle immediately following the return prediction, and normal program flow is resumed. The prediction cache memory also stores branch instruction predictions and branch target addresses.

High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~1011 neuron based) large neural networks.

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Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K/sub gate/ for different target subthreshold leakage currents has been identified.

The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process with read and write times of 1ns and a bit fail rate less than 0.5ppm is reported for the first time. T-RAM memory cell median read current of 250µA/cell at 1.2V with an I on /I off current ratio of more than 108 is demonstrated at 105°C. Robust margins to dynamic disturb due to the access (read/write) of neighboring bits in the memory array have also been verified.

Nihar R. Mohapatra

Papers

High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

32nm high-density high-speed T-RAM embedded memory technology