Patent
EEPROM having coplanar on-insulator FET and control gate
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TLDR
In this paper, an electrically erasable programmable read-only memory (EEPROM) was proposed, which includes a field effect transistor and a control gate spaced apart on a first insulating layer.Abstract:
An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.read more
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Patent
Data storage device and refreshing method for use with such device
P. Fazan,Serguei Okhonin +1 more
TL;DR: In this article, a data storage device such as a DRAM memory having a plurality of data storage cells (10) is disclosed, each data storage cell has a physical parameter which varies with time and represents one of two binary logic states.
Patent
Bipolar reading technique for a memory cell having an electrically floating body transistor
Serguei Okhonin,Mikhail Nagoga +1 more
TL;DR: In this article, the intrinsic bipolar transistor current component is employed to read and/or determine the data state of the electrically floating body memory cell during read operation, and the program window obtainable with this reading technique may be considerably higher than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component).
Patent
Integrated circuit having memory array including ECC and column redundancy and method of operating same
TL;DR: In this article, an integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, coupled with multiplexer circuitry coupled to the memory cell arrays, comprising a data multiplexers, each data multiplerixer having a multiplicity of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory array in response to a write operation, and (ii) a second input to receiving read data which are representative of read data read from memory cells
Patent
Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
TL;DR: In this article, a memory cell array consisting of a plurality of memory cells and a bit line is used to store a data state in an integrated circuit (e.g., a logic device or a memory device).
Patent
Semiconductor memory cell, array, architecture and device, and method of operating same
TL;DR: In this paper, the authors describe a two-transistor memory cell with two transistors (102a, 102b) which store complementary data states (0, l) relative to each other.
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Patent
Nonvolatile semiconductor memory device
TL;DR: In this article, a nonvolatile semiconductor memory device with floating gate type field effect transistors was proposed, where a floating gate electrode faces the second semiconductor region with the insulating film interposed there between, so that charge may be transferred between the floating gate and second semiconductors.