Journal ArticleDOI
Error-Correcting Codes for Byte-Organized Arithmetic Processors
Peter G. Neumann,T.R.N. Rao +1 more
TLDR
A theoretical basis for codes with radix r > 2 which are capable of correcting arbitrary arithmetic errors in any Radix r digit is presented, along with practical considerations regarding their applicability.Abstract:
This paper considers codes with radix r > 2 which are capable of correcting arbitrary arithmetic errors in any radix r digit. If each radix r digit represents a byte of b binary digits (e.g., r = 2b), these codes correct any combination of errors occurring in the b binary digits of any single byte. A theoretical basis for these codes is presented, along with practical considerations regarding their applicability.read more
Citations
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Journal ArticleDOI
Code Constructions for Error Control in Byte Organized Memory Systems
TL;DR: This work construct codes which detect any byte error and correct such errors if they are single random errors, and a subclass of the codes developed is shown to have the additional capability of detecting double errors.
Journal ArticleDOI
SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems
TL;DR: For many byte lengths and code lengths, these codes require fewer check bits or have implementation advantages when compared to other SEC-BED-DED codes.
Proceedings ArticleDOI
A multiplier with multiple error correction capability
TL;DR: Both the intrinsic regularity of the R-Net and its simple internal interconnection scheme make this approach suitable for a practical VLSI implementation.
Proceedings ArticleDOI
Pseudo-functional testing for small delay defects considering power supply noise effects
Feng Yuan,Xiao Liu,Qiang Xu +2 more
TL;DR: This paper proposes novel pseudo-functional testing techniques that generate functionally-reachable test cubes for SDD faults in the circuit by taking the circuit layout information into account and uses ATPG-like algorithm to justify transitions that pose the maximized PSN effects on sensitized critical paths under the consideration of functional constraints.
Journal ArticleDOI
Acceptable Testing of VLSI Components Which Contain Error Correctors
TL;DR: The acceptable testing theorem shows that the use of coding and error correction in conjunction with acceptable testing can significantly increase the yield of VLSI chips without seriously compromising their reliability.
References
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Journal ArticleDOI
The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design
TL;DR: The following aspects of the STAR system are described: architecture, reliability analysis, software, automatic maintenance of peripheral systems, and adaptation to serve as the central computer of an outerplanet exploration spacecraft.
Journal ArticleDOI
Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design
TL;DR: General criteria for cost and effectiveness studies of error codes are developed, and results are presented for arithmetic error codes with the low-cost check modulus 2a-1.
Journal ArticleDOI
Error Detecting and Correcting Binary Codes for Arithmetic Operations
TL;DR: The most important property of the codes derived in this paper is that two numbers, i and j, have coded forms that when added in a conventional binary adder, give a sum C( i)+C(j) that differs from C(i+j), the code for the sum, by (at most) an additive constant.
Journal ArticleDOI
A General Class of Maximal Codes ror Computer Applications
Se June Hong,A.M. Patel +1 more
TL;DR: A new class of codes for single-byte-error correction is presented that the number of check bits are not restricted to the multiples of b as in the case of the codes derived from GF (2b) codes.