Patent
Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
Reads0
Chats0
TLDR
In this paper, a memory controller includes a check/correct circuit and a data remap circuit, coupled to receive an encoded data block from a memory comprising a plurality of memory devices.Abstract:
A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is configured to decode the encoded data block and to detect a failure of one of the plurality of memory devices responsive to decoding the encoded data block. The data remap control circuit is configured to cause a remap of each of a plurality of encoded data blocks to avoid storing bits in the failing memory device. A memory controller may also be configured to detect and correct a first failed memory device and a second failed memory device of the plurality of memory devices.read more
Citations
More filters
Journal ArticleDOI
Phase Change Memory
H P Wong,S Raoux,Sangbum Kim,Jiale Liang,J P Reifenberg,Bipin Rajendran,Mehdi Asheghi,Kenneth E. Goodson +7 more
TL;DR: The physics behind this large resistivity contrast between the amorphous and crystalline states in phase change materials is presented and how it is being exploited to create high density PCM is described.
Patent
System and method for using a memory mapping function to map memory defects
TL;DR: In this article, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements, and the memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.
Patent
High density high reliability memory module with power gating and a fault tolerant address and command bus
TL;DR: In this paper, a high density high reliability memory module with power gating and a fault tolerant address and command bus is presented, which includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length.
Patent
Memory agent with error hardware
TL;DR: In this paper, the error hardware may include logic to classify the errors into different severity levels, control corrective action based on the severity level of errors, and/or perform various levels of reset.
Patent
System, method and storage medium for providing fault detection and correction in a memory subsystem
TL;DR: In this article, a memory subsystem with a memory bus and a memory assembly is described, which includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus.
References
More filters
Book
Error control coding : fundamentals and applications
Shu Lin,Daniel J. Costello +1 more
TL;DR: This book explains coding for Reliable Digital Transmission and Storage using Trellis-Based Soft-Decision Decoding Algorithms for Linear Block Codes and Convolutional Codes, and some of the techniques used in this work.
Journal ArticleDOI
Applications of error-control coding
TL;DR: An overview of the many practical applications of channel coding theory in the past 50 years is presented and examples, both historical and current, are given that typify the different approaches used in each application area.
Patent
Method and apparatus for performing error correction on data read from a multistate memory
TL;DR: In this paper, a method and apparatus for performing error correction on data read from a multistate memory is described, where each cell in a memory device is read to generate a read voltage determined by a state of the cell and one of an ordered succession of encoded signals is selected based on the read voltage.
Patent
Fail-over of multiple memory blocks in multiple memory modules in computer system
TL;DR: In this paper, a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from different memory modules.