Patent
Field effect transistor structure and method for making same
TLDR
An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate is proposed in this article.Abstract:
An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.read more
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Patent
Composite metal and polysilicon field plate structure for high voltage semiconductor devices
Thomas Herman,Alexander Lidow +1 more
TL;DR: In this article, a field plate structure is provided to terminate the electrode of a semiconductor device in a manner to reduce curvature of electric field within the body of the semiconductor devices underlying the electrode and surrounding the electrode.
Patent
Semiconductor devices having an improved gate
Sanae Fukuda,Naoyuki Shigyo +1 more
TL;DR: In this paper, the authors proposed a MOSFET consisting of a silicon substrate 1 having a source/drain region 7b formed in a surface region thereof, an insulating film 3 formed of silicon oxide, and a gate electrode 4a.
Patent
Semiconductor device including an insulative layer having a gap
TL;DR: In this paper, a gap is created between the insulating film and the plated line to avoid a possible separation and/or peeling of the film with respect to the substrate.
Patent
Passivated silicon substrate
TL;DR: In this paper, a passivated silicon substrate structure is described, where a silicon substrate has a surface region (14) covered by a silicon dioxide layer (18) no more than about 1,000 Angstroms thick.
References
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Patent
Method for stabilizing fet devices having silicon gates and composite nitride-oxide gate dielectrics
TL;DR: In this paper, a dry oxygen annealing at temperatures between 970 DEG -1,150 DEG C prior to depositing the silicon gate electrode is applied for a duration of one-half to one hour.
Patent
Integrated circuit fabrication process
TL;DR: In this paper, an integrated circuit of high density is fabricated in a simplified process which allows both the use of multiple conducting layers in a dielectric above a semiconductor substrate, such as polycrystalline silicon (polysilicon) field shield and metal interconnection lines, while also making provision for very precise alignment of subsequent layers to diffusions.
Patent
Silicon dioxide etch rate control by controlled additions of p2 O 2 O3
TL;DR: In this paper, a method of making an integrated circuit in which controlled chemical etching of silicon dioxide layers is achieved by the controlled addition of both phosphorus pentoxide and boron trioxide to the silicon dioxide layer.
Patent
Silicon dioxide etch rate control by controlled additions of p' 2'o' 5 'and b' 2'o' 3'hooker; colin edwin lambert<tomes; derek william
TL;DR: In this paper, a method of making an integrated circuit in which controlled chemical etching of silicon dioxide layers is achieved by the controlled addition of both phosphorus pentoxide and boron trioxide to the silicon dioxide layer.