Patent
Flip-flop circuit
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TLDR
In this paper, a switch circuit is inserted between an input data node and a latch circuit for holding data so as to be conducted for a prescribed period at the time of the rise and fall of clock signals.Abstract:
PROBLEM TO BE SOLVED: To reduce power consumption by controlling a switch circuit inserted between an input data node and a latch circuit for holding data so as to be conducted for a prescribed period at the time of the rise and fall of clock signals. SOLUTION: The delay of the clock signals CKY is larger than the delay of the clock signals CKX and a period when both CKX and CKY become an 'H' level is present at the time of both rise and fall of the clock signals CK. Since all serially connected transistors 25, 26, 27 and 28 are conducted in the period, the normal, and reverse signals of input data are passed through the switch circuit 18 and inputted to the latch circuit 13. Since the latch circuit 13 fetches the input data at the time of both rise and fall of the clock signals CK, this flip-flop circuit is operated at a speed which is the double of the frequency of the clock signals CK. Thus, a clock frequency is reduced by half and the power consumption is reduced.read more
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