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Patent

Flip-flop circuit

Hasegawa Masahiro
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TLDR
In this article, the problem of providing a flip-flop circuit which is not affected by delay in normal operation without being increased in circuit scale when a test is conducted in a through state is addressed.
Abstract: 
PROBLEM TO BE SOLVED: To provide a flip-flop circuit which is not affected by delay in normal operation without being increased in circuit scale when a test is conducted in a through state SOLUTION: A signal which is in phase with a clock signal C and its inverted signal CB are supplied to the transfer gates (12, 13) of a slave latch A signal MC which is outputted by a control circuit 10 composed of a NAND circuit, receiving the clock signal C and a control signal T, and its inverted signal MCB are used as signals for controlling the transfer gates of a master latch so as to put the master circuit in a through state at the time of a test with the control signal

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Patent

Pulse latch circuit and semiconductor integrated circuit

Yasuhisa Shimazaki, +1 more
TL;DR: In this article, a pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode where shifting the test pattern scans data is not performed, is presented.
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Master slave flip-flop circuit functioning as edge trigger flip-flop

Masahiro Araki
TL;DR: In this article, the connection of the first line and disconnection of the second line are performed to change the states of the master and slave latch circuits in response to a clock signal.
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Multi-bit flip-flops and scan chain circuits

Min-Su Kim, +2 more
TL;DR: In this paper, a multi-bit flip-flop operating as a master-slave flipflop may minimize power consumption occurring in a clock path through which the clock signal is transmitted.
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Master slave type flip-flop circuit and latch circuit

Akira Nonaka, +3 more
TL;DR: In this article, the problem of stably holding data in a standby mode was solved by using a NAND circuit NAND 0 to which power is supplied even in the standby mode and performs the gate control of a clock signal CK by a standbymode signal RET.
Patent

Set hardened register

Roy M. Carlson
TL;DR: In this paper, a radiation hardened latch and a method of operation are presented to mitigate SET effects, the latch includes an internally located pulse rejection inverter, which receives an input logic signal, delays it, and compares the delay logic signal to the input logic signals.