Flip-flop circuit

TLDR: In this paper, the authors proposed to prevent the generation of a malfunction without requiring a change of a gate length and a gate width of a transistor, by providing two pieces of composite logic circuits.

Abstract: PURPOSE:To prevent the generation of a malfunction without requiring a change of a gate length and a gate width of a transistor, by providing two pieces of composite logic circuits. CONSTITUTION:The first composite logic circuit 23 in which the first plural OR input terminals are connected to a reset signal input terminal IN3, and the second composite logic circuit 24 in which an output terminal is connected to the second data output terminal OUT2 are provided. When a reset signal 03 is a low level, it is reset, but the reset signal 03 is supplied to all input terminals of a multi-input OR circuit of the composite logic circuits 23, 24. By replacing an input terminal to which a reset signal of a two-input NAND circuit for receiving said reset signal has been inputted, with the multi-input OR circuit, and also supplying the reset signal to all input terminals of the multi-input OR circuit, a logical threshold voltage in the reset signal input terminal can be dropped without changing a gate length and a gate width of a transistor.