Patent
Fully pipelined parallel multiplier with a fast clock cycle
TLDR
In this paper, a fully pipelined parallel multiplier with a fast clock cycle is presented, which consists of three units: a bit-product matrix unit, a reduction unit, and an addition unit.Abstract:
A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit. The addition unit includes one or more stages of addition, with each stage also acting as a pipeline stage. Carry lookahead adder (CLA) circuits are cascaded to perform the addition, with one CLA per addition stage. Results from each addition stage are latched to the next stage using d-type latch circuits. The output from the final stage is the final product of the multiplication.read more
Citations
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References
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Patent
High speed addition using Ling's equations and dynamic CMOS logic
TL;DR: In this article, the authors proposed a direct implementation of Ling's equations in a dynamic CMOS logic environment, where low-order Ling pseudo-carries and group propagate terms are generated in parallel in a single gate delay.
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