Patent
Gated-feedback sense amplifier for single-ended local bit-line memories
TLDR
In this paper, a single-ended input sense amplifier uses a pass device to couple the input local bit line to a global bit-line evaluation node, and the sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit line evaluation node.Abstract:
A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.read more
Citations
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Patent
Device for switching between different reading modes of a non-volatile memory and method for reading a non-volatile memory
TL;DR: In this paper, a memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines.
Patent
Differential sensing circuit with dynamic voltage reference for single-ended bit line memory
Shih-Huang Huang,Rei-Fu Huang +1 more
TL;DR: In this article, the authors presented a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory, where the differential sensing amplifying unit was coupled to the single-end bit line memories and the dynamic voltage generator.
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Data dependent keeper on global data lines
TL;DR: The present disclosure relates to a structure which includes at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation.
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Bias-controlled bit-line sensing scheme for eDRAM
Abraham Mathews,Donald W. Plass +1 more
TL;DR: In this article, a method, memory system and a device for the operating of a bit-line sensing circuit for bias-controlled bitline sensing is presented, which includes an input for receiving a single-ended local bitline signal, and a pass device having a first terminal coupled to the input and a second terminal connected to a global bitline node.
Patent
Comparator circuit with feedback and method of operation
TL;DR: In this article, a comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled with a second input voltage and a second current electrode coupling with a first circuit node.
References
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Patent
Sense amplifier and method for sensing signals in a silicon-on-insulator integrated circuit
TL;DR: An improved sense amplifier ad method for sensing signals in a silicon-on-insulator (SOI) integrated circuit improved the performance of semiconductor memories and other circuits implemented in SOI technology as mentioned in this paper.
Patent
Sensing circuit for a semiconductor memory
TL;DR: In this article, a bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a pre-charge phase of a memory cell sensing operation.
Patent
Stored charge differential sense amplifier
TL;DR: In this article, a differential sense amplifier for semiconductor memory cells is described which uses charge transfer preamplification in combination with a ratioless cross-coupled latch circuit to provide sensing and regeneration of binary information stored in a charge storage device.
Proceedings ArticleDOI
A new contact programming ROM architecture for digital signal processor
TL;DR: A new VIA-2 contact programming ROM architecture for quad level metal (QLM) process was developed, fabricated and tested with 100 MIPS 16 bit fixed point digital signal processor (DSP) to achieve nearly the same density as conventional diffusion programming ROM.
Patent
Multi-Port Dynamic Memory Structures
Wing K. Luk,Brian L. Ji +1 more
TL;DR: In this article, a dynamic random access memory (DRAM) circuit has at least one write bit line, at least two read bit lines, a capacitive storage device, a write access device, and a refresh bypass device.