Hardware Design of Rate Control for H.264/AVC Real-Time Video Encoding

TLDR: The hardware design of rate control for real-time video encoded is proposed, where a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided, and average complexity weight values of frames are used to calculate QP.

Abstract: In this paper, the hardware design of rate control for real-time video encoded is proposed In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences The rate control is designed with the hardware for fast QP decision In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP In addition, the rate control is designed with the hardware for fast QP decision The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture The proposed RC was implemented using Verilog HDL and synthesized with UMC standard cell library The synthesis result shows that the gate count of the architecture is about 191k with 108MHz clock frequency