Proceedings ArticleDOI
Heuristic Minimization of BDDs Using Don't Cares
Thomas R. Shiple,Ramin Hojati,Alberto Sangiovanni-Vincentelli,Robert K. Brayton +3 more
- pp 225-231
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TLDR
A systematic study of the problem of finding a minimum BDD size cover of an incompletely specified function, establishing a unified framework for heuristic algorithms, proving optimality in some cases, and presenting experimental results.Abstract:
We present heuristic algorithms for finding a minimum BDD size cover of an incompletely specified function, assuming the variable ordering is fixed. In some algorithms based on BDDs, incompletely specified functions arise forwhich any cover of the functionwill suffice. Choosing a cover that has a small BDD representation may yield significant performance gains. We present a systematic study of this problem, establishing a unified framework for heuristic algorithms, proving optimality in some cases,and presenting experimental results.read more
Citations
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Book ChapterDOI
Partial-Order Reduction in Symbolic State Space Exploration
TL;DR: This work combines both approaches and develops a method for using partial-order reduction techniques in symbolic BDD-based invariant checking and presents theoretical results to prove the correctness of the method, and experimental results to demonstrate its efficacy.
Journal ArticleDOI
Partial-Order Reduction in Symbolic State-Space Exploration
TL;DR: This work combines both approaches and develops a method for using partial-order reduction techniques in symbolic BDD-based invariant checking, and presents theoretical results to prove the correctness of the method, and experimental results to demonstrate its efficacy.
Proceedings ArticleDOI
Logic synthesis for large pass transistor circuits
TL;DR: This work motivates the need for CAD algorithms for PTL circuit design and proposes decomposed BDDs as a suitable logic level representation for synthesis of PTL networks, and presents a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power.
Book
Constraint-based verification
Jun Yuan,Carl Pixley,Adnan Aziz +2 more
TL;DR: The methodology and state-of-the-art techniques of constrained verification, which is new and popular, and relates constrained verification with the also-hot technology called assertion-based design are covered.
Proceedings ArticleDOI
Advanced Verification Techniques Based on Learning
TL;DR: This work presents a verification method which employs a learning technique based on symbolic manipulation and which can more efficiently learn indirect implications, and a framework in which an indirect implication technique is integrated with an OBDD based verification tool.
References
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Book
Computers and Intractability: A Guide to the Theory of NP-Completeness
TL;DR: The second edition of a quarterly column as discussed by the authors provides a continuing update to the list of problems (NP-complete and harder) presented by M. R. Garey and myself in our book "Computers and Intractability: A Guide to the Theory of NP-Completeness,” W. H. Freeman & Co., San Francisco, 1979.
Journal ArticleDOI
Graph-Based Algorithms for Boolean Function Manipulation
TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Proceedings ArticleDOI
Efficient implementation of a BDD package
TL;DR: A package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation is described, based on an efficient implementation of the if-then-else (ITE) operator.
Proceedings ArticleDOI
Sequential circuit design using synthesis and optimization
E.M. Sentovich,K.J. Singh,Cho W. Moon,Hamid Savoj,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +5 more
TL;DR: SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits.