Patent
III-Nitride Devices and Circuits
Yifeng Wu,Rongming Chu +1 more
TLDR
In this paper, a gate-connected grounded field plate device was used to minimize the Miller capacitance effect in a high voltage depletion mode tiansistor and a low voltage enhancement mode transistor.Abstract:
A Ill-nitride based high electron mobility transistor is described that has a gate-connected grounded field plate The gate-connected grounded field plate device can minimize the Miller capacitance effect The transistor can be formed as a high voltage depletion mode tiansistor and can be used in combination with a low voltage enhancement-mode transistor to form an assembly that operates as a single high voltage enhancement mode transistor.read more
Citations
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Patent
Reverse side engineered iii-nitride devices
TL;DR: In this paper, a group III-nitride devices are described that include a stack of 3-NITR layers, passivation layers, and conductive contacts, including a channel layer with a 2DEG channel, a barrier layer and a spacer layer.
Patent
Enhancement Mode III-N HEMTs
TL;DR: In this article, the concentration of Al in the AlXN layer, the Al XN layer thickness, and the n-doping concentration in the ndoped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2 DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.
Patent
Semiconductor heterostructure diodes
TL;DR: In this paper, a planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconducting layers are presented.
Patent
Semiconductor devices with field plates
Rongming Chu,Robert Coffie +1 more
TL;DR: In this article, a III-N device is described with a 3-N material layer, an insulator layer on a surface of the 3-n material layer and an etch stop layer on an opposite side of the 2-N layer from the III-n layer.
Patent
High voltage iii-nitride semiconductor devices
TL;DR: In this paper, a III-N device is described with a buffer layer, a channel layer and a dispersion blocking layer between the buffer layer and the channel layer, and a compositional difference between the first and second layers induces a 2DEG channel in the first layer.
References
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Patent
Power semiconductor device
TL;DR: In this paper, a gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell, and a buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode.
Patent
Wide bandgap transistor devices with field plates
Primit Parikh,Yifeng Wu +1 more
TL;DR: In this article, a transistor structure comprising an active semiconductor layer with metal source and drain contacts (20, 22) formed in electrical contact with the active layer is described. And a gate contact (26) is formed between the source/drain contacts for modulating electric fields within the active layers.
Patent
Enhancement Mode III-N HEMTs
TL;DR: In this article, the concentration of Al in the AlXN layer, the Al XN layer thickness, and the n-doping concentration in the ndoped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2 DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.
Patent
Semiconductor heterostructure diodes
TL;DR: In this paper, a planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconducting layers are presented.
Patent
Insulated gate e-mode transistors
TL;DR: Enhancement-mode III-nitride transistors that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described in this paper.